An analytical cache model

Abstract

Trace-driven simulation and hardware measurement are the techniques most often used to obtain accurate performance figures for caches. The former requires a large amount of simulation time to evaluate each cache configuration while the latter is restricted to measurements of existing caches. An analytical cache model that uses parameters extracted from address traces of programs can efficiently provide estimates of cache performance and show the effects of varying cache parameters. By representing the factors that affect cache performance, we develop an analytical model that gives miss rates for a given trace as a function of cache size, degree of associativity, block size, subblock size, multiprogramming level, task switch interval, and observation interval. The predicted values closely approximate the results of trace-driven simulations, while requiring only a small fraction of the computation cost.

A new memory monitoring scheme for memory-aware scheduling and partitioning

“…A hit in the cache to the MRU block of some set updates counter (1). A hit in the cache to the LRU block of some set updates counter(D), assuming D-way associativity.…”

“…LRU information for all sets is maintained. A hit to any block within the MRU set updates counter (1). A hit to any block within the LRU set updates counter(S), assuming S sets in the cache.…”

“…Thiébaut and Stone [19] modeled the amount of additional misses caused by context switches for set-associative caches. Agarwal, Horowitz and Hennessy [1] also included the effect of conflicts between processes in their analytical cache model and showed that inter-process conflicts are noticeable for a mid-range of cache sizes that are large enough to have a considerable number of conflicts but not large enough to hold all the working sets. However, these models work only for long enough time quanta, and require information that is hard to collect on-line.…”

“…Since multiple processes or threads 1 can interfere in memory or caches, the performance of a process can depend on the actions of other processes. Despite the importance of optimizing memory performance for multi-tasking situations, most published research focuses only on improving the performance of a single process.…”

PSnAP: Accurate Synthetic Address Streams through Memory Profiles

“…Agarwal [29] suggested the Partial Markov Model (PMM). This model depends on a two state Markov chain, where state 0 produces strided addresses and state 1 produces random.…”