An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks

Cmelik, Robert F.; Kong, Shing I.; Ditzel, David R.; Kelly, Edmund J.

doi:10.1145/106974.107001

Cited by 5 publications

(13 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Total Actual instructions executed. This is equivalent to the Total presented in [1]. This is the data presented in Table 1a.…”

Section: Pa-risc Instruction Frequency Countsmentioning

confidence: 90%

“…While they have many similarities, a few instruction set differences are listed below. The differences listed are at the time the comparison data was produced in April 1991 [1,5,6,7]. Changes to the architectures since then are noted in brackets and documented in references [8,9,10].…”

Section: Architectural Differencesmentioning

confidence: 99%

“…The SPEC89 benchmarks were chosen because these were the only benchmarks for which detailed instruction counts for the MIPS and SPARC architectures have been published [1]. Newer SPEC92 benchmarks have been released, but we do not have access to pathlength or instruction count data for architectures other than PA-RISC.…”

Section: Benchmarks Usedmentioning

confidence: 99%

“…Both the PA-RISC compilers and hardware implementations were chosen to be ones which were contemporary with those used in [1] to collect the MIPS and SPARC data. All of the SPEC89 benchmark programs were compiled with the PA-RISC 1.1 C Compiler, version A.08.54, and PA-RISC 1.1 Fortran Compiler, version A.08.05.…”

Section: Compilers and Hardware Implementationsmentioning

confidence: 99%

“…1.50 1.45 Table 1b: Instructions Executed or Nullified Throughout this paper, all the SPARC data and the detailed instructions counts for MIPS are from [1]. However, the overall totals for MIPS used in Table 1a and 1b are from updated MIPS pathlengths supplied in a posting in the comp.arch newsgroup [3].…”

Section: Overall Spec89 Pathlengthsmentioning

confidence: 99%

See 4 more Smart Citations

Pathlengths of SPEC benchmarks for PA-RISC, MIPS, and SPARC

McMahan

Lee

Digest of Papers. Compcon Spring

View full text Add to dashboard Cite

The total instruction pathlength and instruction frequency counts are measured for the SPEC89 benchmark programs on the PA-RISC architecture and compared with previously published information for the MIPS and SPARC architectures. The PA-RISC architecture typically requires significantly fewer instructions than the other two architectures for the same benchmark. The differences in counts for instruction sub-classes are compared and used to estimate the actual impact of some PA-RISC architectural features designed for pathlength reduction [2].

show abstract

“…Total Actual instructions executed. This is equivalent to the Total presented in [1]. This is the data presented in Table 1a.…”

Section: Pa-risc Instruction Frequency Countsmentioning

confidence: 90%

Section: Architectural Differencesmentioning

confidence: 99%

Section: Benchmarks Usedmentioning

confidence: 99%

Section: Compilers and Hardware Implementationsmentioning

confidence: 99%

Section: Overall Spec89 Pathlengthsmentioning

confidence: 99%

See 3 more Smart Citations

Pathlengths of SPEC benchmarks for PA-RISC, MIPS, and SPARC

McMahan

Lee

Digest of Papers. Compcon Spring

View full text Add to dashboard Cite

show abstract

A Tale of Two Processors: Revisiting the RISC-CISC Debate

Isen

John

2009

Computer Performance Evaluation and Benchmarking

View full text Add to dashboard Cite

Abstract. The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Nowadays, processors with CISC-ISAs translate the CISC instructions into RISC style micro-operations (eg: uops of Intel and ROPS of AMD). The use of the uops (or ROPS) allows the use of RISC-style execution cores, and use of various micro-architectural techniques that can be easily implemented in RISC cores. This can easily allow CISC processors to approach RISC performance. However, CISC ISAs do have the additional burden of translating instructions to micro-operations. In a 1991 study between VAX and MIPS, Bhandarkar and Clark showed that after canceling out the code size advantage of CISC and the CPI advantage of RISC, the MIPS processor had an average 2.7x advantage over the studied CISC processor (VAX). A 1997 study on Alpha 21064 and the Intel Pentium Pro still showed 5% to 200% advantage for RISC for various SPEC CPU95 programs. A decade later and after introduction of interesting techniques such as fusion of micro-operations in the x86, we set off to compare a recent RISC and a recent CISC processor, the IBM POWER5+ and the Intel Woodcrest. We find that the SPEC CPU2006 programs are divided between those showing an advantage on POWER5+ or Woodcrest, narrowing down the 2.7x advantage to nearly 1.0. Our study points to the fact that if aggressive micro-architectural techniques for ILP and high performance can be carefully applied, a CISC ISA can be implemented to yield similar performance as RISC processors. Another interesting observation is that approximately 40% of all work done on the Woodcrest is wasteful execution in the mispredicted path.

show abstract

Branch prediction for network processors

Bermingham¹,

Liu²,

Wang³

et al. 2008

2008 International Conference on Microelectronics

View full text Add to dashboard Cite

Abstract-Meeting the future requirements of higher bandwidth while providing ever more complex functions, future network processors will require a number of methods of improving processing performance. One such method will involve deeper processor pipelines to obtain higher operating frequencies. Mitigation of the penalty costs associated with deeper pipelines have achieved by implementing prediction schemes, with previous execution history used to determine future decisions. In this paper we present an analysis of common branch prediction schemes when applied to network applications. Using widespread network applications, we find that unlike general purpose processing, hit rates in excess of 95% can be obtained in a network processor using a small 256-entry single level predictor. While our research demonstrates the low silicon cost of implementing a branch predictor, the long run times of network applications can leave the majority of the predictor logic idle, increasing static power and reducing device utilization.

show abstract

An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks

Abstract: The dynamic instruction counts of MIPS and SPARC are

Cited by 5 publications

References 3 publications

Pathlengths of SPEC benchmarks for PA-RISC, MIPS, and SPARC

Pathlengths of SPEC benchmarks for PA-RISC, MIPS, and SPARC

A Tale of Two Processors: Revisiting the RISC-CISC Debate

Branch prediction for network processors

Contact Info

Product

Resources

About