An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch

Nikoozadeh, Amin; Murmann, Boris

doi:10.1109/tcsii.2006.883204

Cited by 127 publications

(51 citation statements)

References 9 publications

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“…Senthil Sivakumar M & Banupriya M designed preamplifier based comparators for the Flash ADC design and presented a paper entitled as "High Speed Low Power Flash ADC Design" [3] . In this, pre-amplifier based comparators have been used for ADC architectures such as [6]. The structure of double-tail dynamic comparator first proposed in the paper "A double-tail latch-type voltage sense amplifier with 18ps Setup + Hold time", [7].A double-tail sense amplifier is presented here, which uses one tail for the input stage and another for the latching stage.…”

Section: Literature Surveymentioning

confidence: 99%

Analysis and Design of a New Modified Double-Tail Comparator for High Speed ADC Applications: A Review

Subramanya¹,

Praveen²,

Rao³

2015

International Journal of Innovative Research in Electrical, Ele

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: Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for cost effective data converters that will achieve higher speed and resolution. Comparator is one of the main building blocks in most analog-to-digital converters. Many high speed analog to-digital converters, such as flash ADCs, require high-speed, low power comparators with small chip area. In low power, area efficient, and high speed analog-to-digital converters we need dynamic regenerative comparators to increase speed and power efficiency. In this paper, a new dynamic comparator is proposed, where the circuit of a low voltage low power double tail comparator is modified for area efficient and double edge triggered operation. This paper provides a comprehensive review about a variety of comparator designs -in terms of performance, power and delay using Cadence Virtuoso CMOS 180-nm technology.

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Section: Literature Surveymentioning

confidence: 99%

Analysis and Design of a New Modified Double-Tail Comparator for High Speed ADC Applications: A Review

Subramanya¹,

Praveen²,

Rao³

2015

International Journal of Innovative Research in Electrical, Ele

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“…Capacitive load imbalance on the output nodes also contributes to offset [52]. The offset voltage contribution is usually dominated by mismatches in the input differential pair of the dynamic comparator [51].…”

Section: Offsetmentioning

confidence: 99%

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Harikumar

2014

Linköping Studies in Science and Technology. Thesis

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In today's system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ √ Hz while consuming 6.8 mW.Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium r...

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“…Recently, many comprehensive analyses have been presented, which investigate the performance of these comparators from different aspects, such as noise [11], offset [12], [13], and [14], random decision errors [15], and kick-back noise [16]. In this section, a comprehensive delay analysis is presented; the delay time of two common structures, i.e., conventional dynamic comparator and conventional dynamic double-tail comparator are analyzed, based on which the proposed comparator will be presented.…”

Section: Regenerative Comparators Withmentioning

confidence: 99%

High Speed and Low Power Double-Tail Comparator using Switching Transistor

Balla¹,

YKUNTAM²

2014

International Journal of Advanced Research in Computer and Comm

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Abstract:The high speed conversions are needed in the faster analog -to-digital converters. The accuracy of comparators is defined by its power consumption and speed. Many high speed ADCs, such as flash ADCs, require High speed, Low power comparators with small chip area. Conventional dynamic latched comparators suffer from low supply voltages especially when threshold voltage of the devices is not scaled at the same pace as the supply voltages of the modern CMOS process. The proposed comparator System has lower input-referred latch offset voltage and higher load drivability than the conventional dynamic latched comparators. In the dynamic Double tail comparator the simulation in a CMOS technology. In the Proposed dynamic Double tail comparator System both the power consumption and delay time will be significantly reduced. The maximum clock frequency of the proposed comparator can be reduced at modified supply voltages.

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An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch

Cited by 127 publications

References 9 publications

Analysis and Design of a New Modified Double-Tail Comparator for High Speed ADC Applications: A Review

Analysis and Design of a New Modified Double-Tail Comparator for High Speed ADC Applications: A Review

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

High Speed and Low Power Double-Tail Comparator using Switching Transistor

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