An analog DFE for disk drives using a mixed-signal integrator

Le, M.Q.; Hurst, P.J.; Dyer, K.C.

doi:10.1109/vlsic.1998.688042

Cited by 5 publications

(6 citation statements)

References 12 publications

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“…The dc component of the pulse extraction circuits has been mathematically proved to be equivalent to a bandpass filter bank with central frequencies at , where is positive integer, [1,2,3 ]; the bandpass filters has the shape of function. A 1-ns pulse extractor has been designed and experimentally tested; the design mostly employs standard digital circuit, making it easily scalable to higher speed digital processes above the gigahertz range.…”

Section: Discussionmentioning

confidence: 99%

“…6(b), is the power-spectrum density of a random digital sequence with symbol rate of . The weighting factor is equivalent to a bandpass filter bank with central frequencies at , where is positive integer, [1,2,3 ]; the bandpass filter has the shape of function. The value of the filter is relatively small compared to typical bandpass filters commonly used for power-spectrum estimation.…”

Section: Pulse Extraction Methodsmentioning

confidence: 99%

“…The most widely used adaptation criterion is the mean-square error (MSE) calculated between the recovered signal and the training data in the time domain at sampling points [1], [2]. The typical equalizer structures using this criterion are feedforward transversal equalizers (FFE) and decision-feedback equalizer (DFE) using the least-mean square (LMS) algorithm or its variations [3].…”

Section: Introductionmentioning

confidence: 99%

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A Digital Power Spectrum Estimation Method for the Adaptation of High-Speed Equalizers

Lin

Liu

2004

IEEE Trans. Circuits Syst. I

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This paper presents a new method to estimate the power spectrum of digital signals, which is then used to generate an error signal to tune Gbps data rate equalizers for digital communications. The proposed power spectrum estimation method can be realized with standard digital circuits and has been fabricated and tested in 0.35-m CMOS technology for 1-Gbps data rate. Compared with the traditional bandpass filter followed by a rectifier implementation, this method has wider input signal range and is scalable to higher speed technologies beyond the gigahretz range, in addition to largely reduced power dissipation and die area. Also presented are system simulations on the bit-error rate performance and the error space analysis of the proposed method in comparison with the method of using a bandpass filter followed by a rectifier.

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Section: Discussionmentioning

confidence: 99%

Section: Pulse Extraction Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Digital Power Spectrum Estimation Method for the Adaptation of High-Speed Equalizers

Lin

Liu

2004

IEEE Trans. Circuits Syst. I

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“…3 shows the block diagram of the proposed BCC, which is composed of an RCC and a calibration processor (CP). The CP resembles a discrete-time integrator in the digital domain [12], [13]. The CHP2 chopper in Fig.…”

Section: Random-chopping Comparatormentioning

confidence: 99%

A background comparator calibration technique for flash analog-to-digital converters

Huang

2005

IEEE Trans. Circuits Syst. I

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This paper presents a background calibration technique for trimming the input-referred offsets of the comparators in a flash analog-to-digital converter (ADC) without interrupting the ADC's normal operation. For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. Binary feedback is then used to digitally adjust the comparator's offset so that the offset is minimized. All calibration procedures are performed in the digital domain. The calibration performance is characterized by the converging speed of the feedback loop and the offset fluctuation due to the disturbance of the ADC's input. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of the ADC's input, the BCC's offset quantized step size, and the threshold of an internal bilateral peak detector. The offset fluctuation of a BCC can be drastically reduced by employing a windowing mechanism. The use of windowed BCCs in a flash ADC can introduce nonmonotonic-threshold (NMT) effects which include an increase in calibration settling time and an increase in ( OS ). The use of uncorrelated random chopping for neighboring BCCs can ensure the validity of offset detection and mitigate the NMT effects.

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“…Fortunately, this method also has an important bene fit in that it can also be used to stabilize the behavior of the adaptation. It accomplishes this by using the integrator structures typically present in the sign-sign implementation to reduce the unwanted variations in tap values [19], [20].…”

Section: A Igorithmsmentioning

confidence: 99%

Blind adaptation of a decision feedback equalizer for use in a 10Gbps serial link

Berndt¹

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The Decision Feedback Equalizer (DFE) is commonly used in recovering data at the receive end of a multi-gigabit per second rate serial backplane channel. This form of equalization scheme typically relies on a training sequence. However this training sequence may not be shared by all implementations of the DFE, thus causing significant compatibility issues. A model of a DFE and adaptation algorithm was developed in MATLAB in combination with measurement data of a typical backplane channel. A method was developed to process the incoming signals from the channel involving a known adaptation algorithm in order to determine appropriate tap coefficients. These coefficients are shown to be effective for a data rate of 10 Gbps. The design presented would yield itself to standard-cell implementation except for the analog DFE structure and several stages of the up/down counters. Furthermore the design was evaluated using representative error sources and across several design parameters.Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.There are many people I would like to thank for their encouragement and support during the course of my degree. The first and foremost is my supervisor, Professor Tad Kwasniewski, for always guiding me with my best interests in mind and for creating an environment which is so ideal for learning. I would like to thank my research group, from which I have learned a great deal more than I had ever anticipated. To my friends in the department;

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An analog DFE for disk drives using a mixed-signal integrator

Cited by 5 publications

References 12 publications

A Digital Power Spectrum Estimation Method for the Adaptation of High-Speed Equalizers

A Digital Power Spectrum Estimation Method for the Adaptation of High-Speed Equalizers

A background comparator calibration technique for flash analog-to-digital converters

Blind adaptation of a decision feedback equalizer for use in a 10Gbps serial link

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