An analog approach to "neuromorphic" communication

Marienborg, J.-T.; Lande, Tor Sverre; Abuskand, A.; Høvin, M.

doi:10.1109/iscas.1996.541617

Cited by 6 publications

(3 citation statements)

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“…Let us assume pixel activity is constrained to a normalized unity interval . We want the algorithms to map this activity interval into an event frequency interval , and we want a linear transformation as a VLSI AER system [10]- [27] would do it. For zero pixel activity the output frequency should be zero, and no events are transmitted.…”

Section: Appendixmentioning

confidence: 99%

“…Note that this coding scheme may be highly inefficient for convential image transmission: Monochrome VGA resolution 2 yields a peak rate of (480 640 pixels/frame) (256 spikes/pixel) (25 frames/s) (19bit/spike) 37 Gbit/s. However, most of the AER hardware systems reported so far in literature use this rate-coded AER [7], [8], [10]- [12], [14]- [19], [23], [27], [29], [48], [50], [51]. This is because AER systems do not usually transmit raw images, but already preprocessed images, such as edges or contrast [51] (in which 20 gray levels are satisfactory, and only a small percentage of all pixels-between 1-10%-will present appreciable contrast).…”

mentioning

confidence: 99%

“…In this paper, we will concentrate on rate-coded AER, which is still the most widely reported for AER hardware systems [7], [8], [10]- [12], [14]- [19], [23], [27], [29], [48], [50], [51]. Research for nonrate-coded AER algorithmic generation is presently under development [40]- [43].…”

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confidence: 99%

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On algorithmic rate-coded AER generation

Linares-Barranco

Jiménez-Moreno

Linares-Barranco

et al. 2006

IEEE Trans. Neural Netw.

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This paper addresses the problem of converting a conventional video stream based on sequences of frames into the spike event-based representation known as the address-event-representation (AER). In this paper we concentrate on rate-coded AER. The problem is addressed as an algorithmic problem, in which different methods are proposed, implemented and tested through software algorithms. The proposed algorithms are comparatively evaluated according to different criteria. Emphasis is put on the potential of such algorithms for a) doing the frame-based to event-based representation in real time, and b) that the resulting event streams ressemble as much as possible those generated naturally by rate-coded address-event VLSI chips, such as silicon AER retinae. It is found that simple and straightforward algorithms tend to have high potential for real time but produce event distributions that differ considerably from those obtained in AER VLSI chips. On the other hand, sophisticated algorithms that yield better event distributions are not efficient for real time operations. The methods based on linear-feedback-shift-register (LFSR) pseudorandom number generation is a good compromise, which is feasible for real time and yield reasonably well distributed events in time. Our software experiments, on a 1.6-GHz Pentium IV, show that at 50% AER bus load the proposed algorithms require between 0.011 and 1.14 ms per 8 bit-pixel per frame. One of the proposed LFSR methods is implemented in real time hardware using a prototyping board that includes a VirtexE 300 FPGA. The demonstration hardware is capable of transforming frames of 64 x 64 pixels of 8-bit depth at a frame rate of 25 frames per second, producing spike events at a peak rate of 10(7) events per second.

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Section: Appendixmentioning

confidence: 99%