An analog (7,5) convolutional decoder in 65 nm CMOS for low power wireless applications

IEEE Trans. Circuits Syst. I

et al. 2015

Self Cite

Targeting emerging energy constrained bio-implantable or wearable wireless devices, this work presents design space exploration of decoding circuits for convolutional codes in 65 nm CMOS for ultra-low power operation. Decoders operating in digital and analog domains are designed and measured for energy efficiency, bit error rate (BER) performance and throughput. For the analog decoders which are sensitive to noise and device mismatch, the overall effects of transistor dimensions on the output BER are also investigated. The digital implementation with 0.11 area consumes minimum energy at 0.32 V supply, which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain. Likewise, in analog domain, three decoding circuits are fabricated that share the same topology and design, except for transistor dimensions. The largest analog decoding core (AD1) takes 0.104 and the other two (AD2 and AD3) are 0.035 and 0.015 , respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8 V supply, and 2.3 dB coding gain with 10 pico-Joules per bit (pJ/b) energy efficiency is achieved at 2 Mbps.Index Terms-Circuits and systems for coding in communication systems, circuits for wearable/implantable (bio) electronics, design space exploration, low power design.

Section: B Analog Decoding Circuitmentioning

confidence: 99%

Low Power Analog and Digital (7,5) Convolutional Decoders in 65 nm CMOS

Meraji

Sherazi

IEEE Trans. Circuits Syst. I

et al. 2015

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“…The architecture of the decoder is shown in Fig. 12, whereas the detailed structure is presented in [43].…”

Section: Analog Decodermentioning

confidence: 99%

A Receiver Architecture for Devices in Wireless Body Area Networks

Sjöland

IEEE J. Emerg. Sel. Topics Circuits Syst.

Bryant

et al. 2012

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A receiver architecture suitable for devices in wireless body area networks is presented. Such devices require minimum physical size and power consumption. To achieve this the receiver should therefore be fully integrated in state-of-the-art CMOS technology, and size and power consumption must be carefully considered at all levels of design. The chosen modulation is frequency shift keying, for which transmitters can be realized with high efficiency and low spurious emissions. A directconversion receiver architecture is used to achieve minimum power consumption and a modulation index equal to two is chosen, creating a mid-channel notch in the modulated signal. A tailored demodulation structure has been designed to make the digital baseband compact and low power. To increase sensitivity it has been designed to interface with an analog decoder. Implementation in the analog domain minimizes the decoder power consumption. Antenna design and wave propagation are taken into account via simulations with phantoms. The 2.45 GHz ISM band was chosen as a good compromise between antenna size and link loss. An ultra-low power medium access scheme has been designed, which is used both for system evaluation and for assisting system design choices. Receiver blocks have been fabricated in 65-nm CMOS, and an RF front-end and an analogto-digital converter have been measured. Simulations of the complete baseband have been performed, investigating impairments due to 1/f noise, frequency and time offsets. Index Terms-Body sensor networks, CMOS integrated circuits, Low power electronics, Receivers, System-on-a-chip I. INTRODUCTION HERE are numerous applications for ultra-low power wireless communication. For instance, it can benefit such different areas as health care [1] and smart buildings [2], [3]. To achieve ultra-low power consumption it is important to combine low-power transceiver circuits with optimized communication protocols. In medical implants this is critical Manuscript received October 6, 2011.

“…Precise evaluation of these decoding circuits is best to be performed by chip measurements. Following the background theory and architecture description that have been reported in [6] and follow up simulations that has been performed in [7], [5] to cope with technical challenges and choose design parameters, an analog decoder was eventually fabricated in 65 nm CMOS technology. Here, the measurement results are presented to conclude the work.…”

Section: Introductionmentioning

confidence: 99%

A 3μW 500 kb/s ultra low power analog decoder with digital I/O in 65 nm CMOS

Meraji

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

Sjöland

et al. 2013

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Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)8 convolutional codes and takes 0.104 mm 2 on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 µW the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.