An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor

Rahman, Fahim; Kim, Sung Hoon; John, Naveen; Kumar, Roshan; Xi, Li; Pamula, Rajesh; Bowman, Keith; Sathe, Visvesh

doi:10.1109/vlsic.2018.8502303

Cited by 6 publications

(2 citation statements)

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“…Comparisons with other clocking stretching circuits [3], [4], [6] are shown in Table I. Some works provided bi-directional clocking to follow the supply droop [36]- [38], [42], [43]. Most of the current adaptive clocking circuits need one or more clock cycles for tuning, while ours has zero latency that it is able to stretch the clock cycle at the current cycle.…”

Section: B Measurement Of the Adaptive Clocking Circuitmentioning

confidence: 99%

“…Besides these droop detection-based adaptive clock stretching circuits, there are adaptive frequency/voltage tracking circuits [36]- [38], which may either decrease or increase the frequency in response to the supply droop. Recently, unified voltage and frequency regulators were proposed to let the supply voltage recover from the droop besides tuning the frequency [42], [43].…”

Section: Introductionmentioning

confidence: 99%

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A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System

Shan

Dai

Wan³

et al. 2020

IEEE J. Solid-State Circuits

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Resilient circuits based on in situ timing monitoring adaptive voltage-frequency scaling (AVFS) eliminate excess time margins caused by process, voltage, and temperature (PVT) variations but suffer from 50% throughput loss during error recovery when operating at a half frequency. We propose a bi-directional adaptive clocking circuit to provide fine frequency tuning with zero latency for AVFS system. It can either stretch the clock cycle when there are timing errors to ensure correct function or compress the cycle when there are excess timing margins. To support a wide frequency range, we generate multiple phase clocks based on two delay lines and select one appropriate phase clock to obtain a stretched output clock, where balanced clock paths are obtained by a time-to-digital converter and dynamic-OR gates. Applied to a wide-operating-range AVFS system of an SHA-256 accelerator with transition detector (TD) latches, the whole AVFS system is able to respond to errors in one clock cycle, with dynamic-OR gates collecting all the errors in half a cycle and adaptive clocking circuit stretching at the current cycle. Fabricated in 28-nm CMOS, chip measurement shows that it achieves 38.6%-69.4% power gains at near threshold while reducing throughput loss during error recovery.

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