An All-Digital Fused PLL-Buck Architecture for 82% Average <i>V</i>
                  <sub>dd</sub>-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Sun, Xun; Rahman, Fahim; Pamula, Venkata Rajesh; Kim, Sung; Li, Xi; John, Naveen; Sathe, Visvesh

doi:10.1109/jssc.2019.2936968

Cited by 10 publications

(3 citation statements)

References 17 publications

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“…To minimize the guardband, it was proposed recently to combine the V REG and F REG regulation loops into a single unified loop. This loop can be based on an LDO [65], switched capacitor [64], or buck converter [66]- [68]. Buckand LDO-based UVFRs are shown in Fig.…”

Section: B State-of-the-art Uvfrsmentioning

confidence: 99%

“…Thus, these margins are significantly reduced by using UVFRs. For instance, the UVFR in [66] achieved 96% of margin recovery even though the loop bandwidth was well below 1 MHz. It reduced the processor's overall energy consumption by 48% while supplying V DD of 1.0V.…”

Section: B State-of-the-art Uvfrsmentioning

confidence: 99%

“…Unified V DD and F CLK regulation loops based on (a) buckconverter[66] and (b) digital LDO (DLDO)[65].…”

mentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality finegrained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transientboost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current. INDEX TERMS Power delivery network (PDN); fine-grained power management; dynamic-voltage and frequency scaling (DVFS); dynamic-voltage scaling (DVS); low-dropout regulator (LDO); digital LDO; unified-voltage and frequency regulator (UVFR); frequency-referenced digital LDO (FR-DLDO); transientboost control.

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Section: B State-of-the-art Uvfrsmentioning

confidence: 99%

Section: B State-of-the-art Uvfrsmentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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A high efficiency buck converter based on PLL for frequency stabilization

Yang,

Wu,

Zhang

et al. 2023

Microelectronics Journal

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Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS

Rahman

Pamula

Sathe

2020

IEEE J. Solid-State Circuits

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An All-Digital Fused PLL-Buck Architecture for 82% Average V _dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Cited by 10 publications

References 17 publications

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

A high efficiency buck converter based on PLL for frequency stabilization

Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS

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An All-Digital Fused PLL-Buck Architecture for 82% Average V dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Cited by 10 publications

References 17 publications

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

A high efficiency buck converter based on PLL for frequency stabilization

Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS

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Product

Resources

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An All-Digital Fused PLL-Buck Architecture for 82% Average V _dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor