An all-digital A/D converter TAD with 4-shift-clock construction for sensor interface in 0.65-&amp;#x03BC;m CMOS

2010 17th IEEE International Conference on Electronics, Circuits and Systems

Terasawa

2010

Self Cite

An all-digital TAD-OFDM detection method for sensor interface with digital synchronous detection based on TAD (Time AID converter)-type ADC is introduced. A TAD basic structure is a completely digital circuit including a ring delay-line (RDL) with delay units (DUs) driven by an input voltage Vio and an RDL frequency counter, latch and encoder. Since the operating principle is to count the number of DUs through which the delay pulse passes within a sampling period T., this ADC (TAD) naturally performs as a Vio voltage integration circuit for T •. Hence, high frequency noises can be removed simultaneously with AID conversion. First, as an example of a voltage-integration effect as a low-pass tiIter, magnet pick-Up sensing was verified using a 22-bit TAD test chip fabricated using a 0.65-Jlm CMOS with 106 JlV/LSB (100 kS/s). Next, the idea of digital synchronous detection with TAD (called TAD-DSD with the voltage-integration effect) is proposed. Finally, by using the TAD-DSD principle, TAD OFDM detection is presented and experimentally confirmed, resulting in signal-detection of each wave-amplitude from a four-carrier-composite wave, which consists of frequencies, 1.6-, 3.2-, 6.4-and 12.8-MHz, respectively.

Section: Tad Operation and Adc Performancementioning

confidence: 98%

All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detection

2010 17th IEEE International Conference on Electronics, Circuits and Systems

Terasawa

2010

Self Cite

“…2 is the front-end of the 2-CKES architecture, which is modified from the 4-TAD-composite ADC core block diagram of the front-end of the CKES construction in [10]. Since the CKES method is based on alldigital circuits as explained in [10] with a 0.65-μm digital CMOS, using 0.35-μm CMOS with the CKES method is supposed to be almost automatically possible even for use in high temperature. A single ring-delay-line (RDL) consisting of 16 delay units (DUs) and single RDL-counter are shared by two TAD modules, which consist of two "Latch & Encoder sections," and two latches input the RDL-counter output data.…”

Section: A 2-ckes Circuit Configrationmentioning

confidence: 99%

All-Digital A/D converter TAD for sensor interface over wide temperature ranges

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

Isomura

Terasawa

2012

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For achieving a highly-durable sensor ASIC with high performance and low cost, an all-digital sensor ADC using a time-domain processor TAD (Time A/D converter) is presented. Generally, measuring travel time of signals (e.g., light pulses, radio and ultrasonic waves, etc.) should be done under various stringent conditions (i.e., high ambient temperature) in automobiles, heavy-machinery and resource exploration systems, for example. Therefore, to realize wide-range temperature durability, sensor ADC circuits should be fully-digital, including a ring-delay-line (RDL) driven by an input voltage V in for its power supply, along with an RDL frequency counter, latch and encoder. In this study, an ADC core is implemented with 0.26 mm 2 in a low-cost 0.35-μm digital CMOS applying our original 2-CKES (clock edge shift) method for higher resolution. When detecting low-level noisy signals received, a high-speed sensor ADC with a voltage resolution of 10.9 mV/LSB (6.5bit, 40MS/s) is available for integrating received pulse/wave amplitude to determine signal-travel time in a wide temperature range between -40 and 125°C. In addition, the all-digital architecture TAD is suitable for porting and scaling to another silicon technology with minimal IC design term and cost. As a scaling result, using a test-IC in a 0.18-μm digital CMOS, we have also experimentally confirmed its stable operations between -40 and 125°C with a smaller active area (0.044mm 2 ) and higher resolutions, resulting in 0.15mV/LSB (1MS/s).

“…Under these circumstances, we have developed an alldigital ADC [4CKES (4-clock-edge-shift) TAD] in a 65nm digital CMOS for both high-resolution and low-power operation simultaneously, proving high scalability of TAD from 0.65µm-CMOS TAD [7] achieving around 100 times smaller core area. Indeed, traditional ADC architectures always require severe redesign with very hard work for CMOS scaling.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, since there are few delay units in the RDL, a small-sized buffer can be used to avoid loading the signal (V in ) as an impedance converter, if necessary. This is because both high-and lowfrequency noise due to the buffer can be removed by TAD-filter effect [3] and digital post-processing [digital CDS (correlated double sampling) method] as explained in [5], [7], respectively.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

All-digital 0.016mm<sup>2</sup> reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Miyahara

et al. 2014

Self Cite

An all-digital reconfigurable (10-to-16-bit) sensor ADC based on TAD (Time A/D converter) is completely digital, using a ring-delay-line RDL driven by an input voltage V in as its power supply. This method realized 16.2bit/100ksps/37.5μW from 0.6V supply without any static current using a 0.016mm 2 prototype 4CKES (4-clock-edge-shift) TAD in a 65nm digital CMOS. Resolutions can be controlled by setting its conversion time T cv . A 13.8bit/1Msps/75.4μW or 10.5bit/10Msps/93.2μW operation is also experimentally confirmed using 0.6V supply. Finally, correction of nonlinearity characteristics has been discussed using differential-setup processing method. I.978-1-4799-4242-8/14/$31.00 c 2014 IEEE