An Algorithm for Improving the Throughput of Serial Low-Complexity Chase Soft-Decision Reed–Solomon Decoder

Luo, Haowen; Zhang, Wei; Wang, Yang; Yan, Hu; Liu, Yanyan

doi:10.1109/tvlsi.2017.2746139

Cited by 3 publications

(2 citation statements)

References 15 publications

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“…In Fig. 19, we compare the gate count (#XORs) and coding gain of the proposed decoders with the results from state-of-the-art soft-decision RS(255,239) decoders, specifically η=3 LCC based on HDD [7], Factorization-Free decoder (FFD) [12], Interpolation-Based decoder (IBD) [13], Decision-Confined Decoder (DCD) [9], Early-Termination LCC Decoder (ETD) [14] and our η=4 LCC [10]. As can be seen, the proposed decoder has a coding gain of 0.56 at FER=10 −6 with respect to a HDD while the best alternative, the η=4 LCC from [10], has a coding gain of 0.45 (see Fig.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…The Vector Selection block also outputs the identification number of the test vector that is selected. FFD[12] DCD [9] IBD [13] ETD [14] η=4 [10] # XORs (•10 3 ) Coding Gain (dB) Figure 19: Coding gain at FER=10 −6 versus implementation cost (#XORs) for ASIC devices. Note: data from the decoders labeled as η=3 [7], FFD [12], IBD [13] and ETD [14] are estimations and do not include the multiplicity assignment stage.…”

Section: Vector Selection Blockmentioning

confidence: 99%

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A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed–Solomon Decoding

Valls

Torres

Canet

et al. 2019

IEEE Trans. Circuits Syst. I

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This work presents a Low-Complexity Chase (LCC) Decoder for Reed-Solomon (RS) codes, which uses a novel method for the selection of test vectors that is based on the analysis of the symbol error probabilities derived from simulations. Our results show that the same performance as the classical LCC is achieved with a lower number of test vectors. For example, the amount of test vectors is reduced by half and by 1/16 for the RS(255,239) and RS(255,129) codes, respectively. We provide evidence that the proposed method is suitable for RS codes with different rates and Galois Fields. In order to demonstrate that the proposed method results in a reduction of the complexity of the decoder, we also present a hardware architecture for an RS(255,239) decoder that uses 16 test vectors. This decoder achieves a coding gain of 0.56 dB at FER=10 −6 compared to hard-decision decoding, which is higher than that of an η=5 LCC. The implementation results in ASIC show that a throughput of 3.6 Gbps can be reached in a 90 nm process and 29.1 KXORs are required. The implementation results in Virtex-7 FPGA devices show that the decoder reaches 2.5 Gbps and requires 5085 LUTs.

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Section: Implementation Resultsmentioning

confidence: 99%

Section: Vector Selection Blockmentioning

confidence: 99%

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed–Solomon Decoding

Valls

Torres

Canet

et al. 2019

IEEE Trans. Circuits Syst. I

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Development and Validation of an optimized syndromes block for reed solomon decoder

Mohamed,

Azeddine,

Anas El Habti

et al. 2023

ITM Web Conf.

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Reed Solomon decoder plays an indispensable role in many applications involving data transmission, storage applications and Video broadcasting DVB-T and DVB-S2. In this work we propose a new optimized parallel syndrome block [67] for the Reed Solomon RS code (15,11) used in digital Video broadcasting DVB-T. Therefore, this proposed parallel block is compared to the serial syndrome block existing. On the basis of this technique a new architecture based on three syndromes in parallel is developed. This technique reduces both the energy consumption and the number of iterations. The RS code (15, 11) is composed of 255 symbols that are multiples of 3. The symbols are entered in parallel in the syndrome block. These decoding algorithms developed in this work are compared with the existing algorithms, and they are evaluated through a simulation using the hardware description language VHDL, then they are implemented on a Xilinx Spartan type FPGA card using the XILINX software.

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Low-Complexity Chase Decoding of Reed–Solomon Codes Using Channel Evaluation

Wang

Zhang

Chang

et al. 2022

Entropy

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A novel time-varying channel adaptive low-complexity chase (LCC) algorithm with low redundancy is proposed, where only the necessary number of test vectors (TVs) are generated and key equations are calculated according to the channel evaluation to reduce the decoding complexity. The algorithm evaluates the error symbol numbers by counting the number of unreliable bits of the received code sequence and dynamically adjusts the decoding parameters, which can reduce a large number of redundant calculations in the decoding process. We provide a simplified multiplicity assignment (MA) scheme and its architecture. Moreover, a multi-functional block that can implement polynomial selection, Chien search and the Forney algorithm (PCF) is provided. On this basis, a high-efficiency LCC decoder with adaptive error-correcting capability is proposed. Compared with the state-of-the-art LCC (TV = 16) decoding, the number of TVs of our decoder was reduced by 50.4% without loss of the frame error rate (FER) performance. The hardware implementation results show that the proposed decoder achieved 81.6% reduced average latency and 150% increased throughput compared to the state-of-the-art LCC decoder.

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An Algorithm for Improving the Throughput of Serial Low-Complexity Chase Soft-Decision Reed–Solomon Decoder

Cited by 3 publications

References 15 publications

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed–Solomon Decoding

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed–Solomon Decoding

Development and Validation of an optimized syndromes block for reed solomon decoder

Low-Complexity Chase Decoding of Reed–Solomon Codes Using Channel Evaluation

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