An algorithm for exact bounds on the time separation of events in concurrent systems

Abstract

Determining the tzme separation of events as u firnduinental problem in the unulysis, synthesis, und optimizution of concvrrrnt systems. Applicutions runye from logic nptimizutron of asynchronous diyitul circiizts to evuliiution of e x e c d o n timtts of proyrums f o r real-time systems. W e present u n eficient ulyorithm t o find exuct (tight) boimds on the separation time of t : w nts i n an arbitrury process yruph without conditionul behuvior. The algorithm is bused on U fiinctional dec,omposition technique that permits the implicit evciliiufion of uii infinitely unfolded process gruph. 1ntrodu.ctionIn this paper, we derivt. an exact, algorithn that dei ermines tight, upper and lower boiinds on the separation in time of an arbitrary pair of system eventls. Depending on the level of ahstaraction in the specification, events may represent, low-level signal transitions at, a circuit, interface or control flow in a more abstr;zct behavioral view. If we are able to determine t,ht. bounds on. the separation in time of two events tht'n we can iise this information to: simplify cornhinat.ional and sequentd logic by extracting t,emporal don't, care information, verify that ii logic implement,at.ion meets specified timing constrairit,s, identify and remove hazards from asynclironous circuits, and fociis opi.imization efforts in data-path synthesis by generat,-ing useful scheduling constraints. Thris, det,ermining t,htb time separation of event,s is a fiintlarnent,al problrm in hhe analysis, synthesis, and optimizat,ion of conciirrent systems.We develop an efficient, solution for determining t,inie ~eparation bounds and also t8aki3 into account, tohe effvcts of starting thr system from a specific reset, or start state. We model a concurrent system as a cyclic connected graph. The nodes of the graph represent events and the arcs are annotated with lower and upper bounds on delays between events. Currently, our solution is limited t,o graphs without, conditional behavior. However, that, stsill leaves a large and useful class of conciirrent, specifications t80 which our analysis applies.Other approaches to the problem of finding bounds on the separation in time of two events have either been inexac.t, or based on a more restrictive graph topology. Loose hounds t9hatl may not, enable all possible optimizations were obtained by [8]. Both [7] and[IO] can only handle acyclic graphs, and [a] only supports a 1imit.ed form of synchronization and conciirrency.This paper is corriposrd of five sections. We follow this int,rotliict.iori witch a formalization of the problem, a review of t,he foundation provided by the solution for finite acyclic graphs, and some examples. Section 3 provides t,he cletsails of our algorithm, which is based on a striic.tjural decomposition of the unfolded process graph. Some practical examples are presenked in Section 4, and finally, Section 5 summarizes the contributions of this paper. P r o b l e m FormalizationConsider a simplr roriciirrrnt system consisting of thrrr proresst~s tliat synchronize over ...

Supervisory control of real-time discrete-event systems using lattice theory

“…Let X be an idempotent commutative monoid as considered in Section II. The operation induces a partial order on X de ned by (1). For any pair in X the least upper bound with respect to this order or supfx; yg is given by x y.…”

An efficient algorithm for time separation of events in concurrent systems

“…Four sets of test cases were used: (i) different variations of asynchronous FIFO designs; (ii) an asynchronous Huffman decoder design from [2]; (iii) designs from the published literature [1], [8] (iv) variants of the examples shown in Section III of this paper.…”

Timing analysis for synthesis in microprocessor interface design

“…The interface design problem arises during system integration when components are blended into a single entity. In general the design of an interface involves not only electrical and logical signal conditioning but also protocol con- In a related direction, STG'S have been extended with timing constmcts to support the description of both synchronous and asynchronous circuits in [12,11,7]. Their approach differ from other timed Petri net formalisms (cf.…”

“…Not every interpretation of a Petri net describes a correct behavior of a circuit (e.g., if two successive transitions of the Petri net are labelled with the same signal transition). KJsually the validity of an STG is checked by ensuring that rhe corresponding state graph is consistent [12]. In the sequel we consider the subclass of STG'S whose underlying Peti nets are mmked graphs that satisfy:…”