An Algorithm Based on AVS Encoding on FPGA Multi-Core Pipeline

Fang, Ji; Li, Xingyuan; Yang, Changlong

doi:10.1109/iccis.2013.400

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…Ji et al [23] proposed an H264/AVC encoder on an MPSOC platform using GOP level parallelism approach. They build three Microblaze soft cores based on XILINX FPGA.…”

Section: Related Workmentioning

confidence: 99%

“…Multi-processor, multicore, multithreading encoding system and parallel algorithms have been discussed in many papers [9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. This paper presents the frame level parallelism (FLP) approach and describes its complete implementation for H.264/AVC encoder using a multicore DSP TMS320C6472.…”

Section: Introductionmentioning

confidence: 99%

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Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera

Bahri

Belhadj²,

Grandpierre³

et al. 2014

J Real-Time Image Proc

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International audienceThe latest generation of multicore digital signal processors (DSP), their high computing power, low consumption, and integrated peripherals will allow them to be embedded in the next generation of smart camera. Such DSPs allow designers to evolve the vision landscape and simplify the developer’s tasks to run more complex image and video processing applications without the need to burden a separate personal computer. This paper explains the exploitation of the computing power of a multicore DSP TMS320C6472 to implement a real-time H264/AVC video encoder. This work can be considered as a milestone for the implementation of the new High Efficiency Video Coding standard (HEVC-H265). In fact, to improve the encoding speed, enhanced Frame Level Parallelism (FLP) approach is presented and implemented. A real-time fully functional video demo is given, taken into account video capture and bitstream storage. Experimental results show how we efficiently exploit the potentials and the features of the multicore platform without inducing video quality degradation in terms of PSNR or bitrate increase. The enhanced FLP using five DSP cores achieves a speedup factor of more than four times in average compared to a mono-core implementation for Common Intermediate Format (CIF 352 × 288), Standard Definition (SD 720 × 480), and High Definition (HD 1280 × 720) resolutions. This optimized implementation allows us to meet the real-time compliant by reaching an encoding speed of 99 f/s (frame/second) and 30 f/s for CIF and SD resolutions respectively, and saves up to 77 % of encoding time for HD resolution

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“…Ji et al [23] proposed an H264/AVC encoder on an MPSOC platform using GOP level parallelism approach. They build three Microblaze soft cores based on XILINX FPGA.…”

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera

Bahri

Belhadj²,

Grandpierre³

et al. 2014

J Real-Time Image Proc

View full text Add to dashboard Cite

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Embedded Real-Time H264/AVC High Definition Video Encoder on TI’s KeyStone Multicore DSP

Bahri

Grandpierre

Ayed

et al. 2016

J Sign Process Syst

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To overcome high computational complexity of advanced video encoders for emerging applications that require real-time processing, using multicore technology can be one of the promising solutions to meet this constraint. In this context, this paper presents a parallel implementation of the H264/AVC high definition (HD) video encoder exploiting the power processing of eight-core digital signal processor (DSP) TMS320C6678. GOP Level Parallelism approach is used to improve the encoding speed and meet the real-time encoding compliant. A master core is reserved to handle data transfer between the DSP and the camera interface via a Gigabit Ethernet link. Multithreading algorithm and ping-pong buffers technique are used to enhance the classic GOP level parallelism approach and hide communication overhead. Experimental results on seven slave DSP cores, running each at 1 GHz, show that our implementation allows performing a real-time HD (1280x720) video encoding. The achieved encoding speed is up to 28 f/s. The proposed parallel implementation accelerates the encoding process by a factor of 6.7 without inducing quality degradation in terms of PSNR or bit-rate increase compared to single core implementation. Experiments show that our proposed scheduling technique for hiding communication overhead allows saving up to 36% of the fully encoding chain time which includes frames capturing, frames encoding and bitstream saving in a file.

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An Algorithm Based on AVS Encoding on FPGA Multi-Core Pipeline

Cited by 2 publications

References 3 publications

Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera

Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera

Embedded Real-Time H264/AVC High Definition Video Encoder on TI’s KeyStone Multicore DSP

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