An advanced submicron CMOS technology with 2&amp;amp;#181;m pitch at all levels

El-Diwany, M.; Brassington, M.P.; Razouk, R. R.; Castel, Egil D.; Sharma, Navneet; Ray, Alan B.; Riley, Paul E.; Kulkarni, Vivek D.; Pierce, J.; Barry, M. L.

doi:10.1109/iedm.1987.191592

Cited by 2 publications

(4 citation statements)

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“…This allayed our initial concerns about the potential detrimental effects of plasma processing during pillar and metal patterning and dielectric planarization. In addition, no deterioration in device reliability was observed in comparison to the conventional contact technology (20). A propagation delay of approximately 100 ps/stage at Vet = 5V was measured for a 2 ~m pitch ring oscillator (20) and is an indication of the enhanced circuit performance which m a y be realized with this technology.…”

Section: Electrical Resultsmentioning

confidence: 86%

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A Scalable Multilevel Metallization with Pillar Interconnections and Interlevel Dielectric Planarization

Castel

Kulkarni

Riley

1990

J. Electrochem. Soc.

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A multilevel metallization system, which results in smooth topography and high packing density by overcoming many of the limitations of the conventional approach, has been developed. In this scheme metallic pillars are used for interlevel wiring, instead of traditional contacts and vias. Refractory metal layers are employed at all levels as an etch stop/ diffusion barrier with a self-aligned metal silicide used to insure low contact resistance between conductor (aluminum) and silicon substrate. Planarized SiO2 is used as the dielectric at each level in which planarization of the dielehtric and exposure of the underlying metallization are achieved by the etchback technique using sacrificial photoresist films. This interconnection scheme can be extended to any number of levels of interconnection and may be readily scaled for use in submicron ULSI technologies.

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Section: Electrical Resultsmentioning

confidence: 86%

“…The topography on the wafer is that which results from the standard processing used to fabricate MOS devices and includes self-aligned titanium silicide over the source/ drain areas and polysilicon gates (20).…”

Section: Process Descriptionmentioning

confidence: 99%

A Scalable Multilevel Metallization with Pillar Interconnections and Interlevel Dielectric Planarization

Castel

Kulkarni

Riley

1990

J. Electrochem. Soc.

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“…P-type silicon wafers, 100 mm diam, were processed through a CMOS process flow described in Ref. (10). The NMOS and PMOS devices had self-aligned titanium silicide in the source, drain, and polysilicon (gate) regions.…”

Section: Methodsmentioning

confidence: 99%

“…An alternative scheme is a quasi-multilayer process called contrast enhancement lithography (CEL) technique (9), which employs a thin layer of contrast enhancing material containing a highly opaque but readily photobleachable dye on top of the photoresist. We have optimized this technique and used it successfully for defining resist pillars and conductor features in the multilevel interconnection scheme developed as part of an advanced submicron CMOS process technology (10).…”

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confidence: 99%

Patterning of Submicron Metal Features and Pillars in Multilevel Metallization

Kulkarni¹,

Sharma²

1988

J. Electrochem. Soc.

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A novel multilevel interconnect scheme has been developed as part of an advanced submicron CMOS process technology. A salient feature of this interconnect scheme is the use of metal pillars for vertical connections between the devices on the substrate and the first level of metallization, as well as between successive levels of metallization, in place of the conventional etched contacts and vias. The pillar and conductor levels, with feature dimensions below 1 μm, were defined using contrast enhancement lithography and reactive ion etching. The application of these techniques to the definition of small and sparse photoresist features on an uneven metallic substrate and to the subsequent pattern transfer to the underlying metal films is described. The issues of surface topography and reflectivity, small‐area photoresist coverage, and dimension and profile control in the patterning of submicron features are addressed.

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An advanced submicron CMOS technology with 2&#181;m pitch at all levels

Cited by 2 publications

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A Scalable Multilevel Metallization with Pillar Interconnections and Interlevel Dielectric Planarization

A Scalable Multilevel Metallization with Pillar Interconnections and Interlevel Dielectric Planarization

Patterning of Submicron Metal Features and Pillars in Multilevel Metallization

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