IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)
DOI: 10.1109/iwipp.2000.885167
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An advanced approach to power module packaging

Abstract: The advanced power electronic packaging technology developed at GE CRD eliminates the need for wire bonds, offers low inductance striplined power electrodes, and low parasitic impedance. In addition, the planarity of the top layer structure and the thermal base provide double-sided cooling capability and improve the size, weight, cost, and thermal and electrical performance of the package.

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Cited by 14 publications
(4 citation statements)
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“…Wire-bondless technologies have led to several novel packaging designs, the most notable of which create a dual-sided package architecture. Figure 2-3 shows a package designed using flip chip technology, which allows for the wire-bonds to be replaced with solder bumps, allowing for applying base plates to both sides to aid in stability [18]. Figure 2-5 shows a single chip that is incorporated into an Embedded Power Chip Module (EPCM), which replaces the conventional wire-bonds with a metallization layer and provides a heat path for topside cooling [19].…”
Section: Power Electronic Packagingmentioning
confidence: 99%
See 1 more Smart Citation
“…Wire-bondless technologies have led to several novel packaging designs, the most notable of which create a dual-sided package architecture. Figure 2-3 shows a package designed using flip chip technology, which allows for the wire-bonds to be replaced with solder bumps, allowing for applying base plates to both sides to aid in stability [18]. Figure 2-5 shows a single chip that is incorporated into an Embedded Power Chip Module (EPCM), which replaces the conventional wire-bonds with a metallization layer and provides a heat path for topside cooling [19].…”
Section: Power Electronic Packagingmentioning
confidence: 99%
“…where ηo is the overall fin efficiency, At is the total surface area of the fins, and Ab is the area of the prime surface [18]. The heat transfer coefficient (h) was solved for using the Nusselt number (Equation 9):…”
Section: Heat Transfer Coefficientmentioning
confidence: 99%
“…Instead, it is preferable to develop a module package with lower parasitic inductances. Several research groups and manufacturers have proposed to reduce the package inductance by replacing the traditional wire bond interconnections with ribbon [42], [43]; flexible PCB [44], [45], [46], [47], [48], solid posts, shims, or bumps [49], [50], [51]; solder balls [52]; directbonded solder [53]; or vias in PCB or ceramic substrates [54], [55], [56], [57]. Several packages also include integrated decoupling capacitors to mitigate the impact of stray inductances [55], [58], [59], [60], [61].…”
Section: Introductionmentioning
confidence: 99%
“…In these cases, the power semiconductor die must be fabricated with solderable front metals (SFMs), such as described in [15]. Another planar interconnect can be built up by deposited metallization onto dies usually embedded in a substrate [16]. Compared with multiple round wires, the large area planar contacts and thick conductor of these new interconnection schemes help reduce the parasitic electric resistance and inductance.…”
Section: Introductionmentioning
confidence: 99%