An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications

Lee, M.-J.E.; Dally, William J.; Poulton, John W.; Chiang, Patrick; Greenwood, S.

doi:10.1109/vlsic.2001.934223

Cited by 27 publications

(8 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1) [1]. To cope with the trend in data communication, several standards for high-speed input-output (I/O) such as PCI-X, PCI-Express and serial ATA have emerged to improve the I/O performance across a broad range of platforms such as desktop, mobile, server communications, workstations and embedded devices [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Design of high-speed clock and data recovery circuits

Kok-Siang

Sulaiman

Hean-Teik

et al. 2007

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR architecture, is addressed. The descriptions start with the most basic XOR logic up to the phasefrequency detector circuit. Trade-offs of each of the phase detectors are outlined. Two types of dual loop CDR architecture are briefly introduced. Finally, full-rate and half rate CDR architectures are described.

show abstract

Section: Introductionmentioning

confidence: 99%

Design of high-speed clock and data recovery circuits

Kok-Siang

Sulaiman

Hean-Teik

et al. 2007

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…The area affected includes chip-to-chip interconnect applications [1]- [2]. Due to this rapid growth, several standards for high-speed I/O such as PCI-X, PCIExpress and serial ATA have emerged with the objective of improving I/O performance across a broad range of platforms.…”

Section: Introductionmentioning

confidence: 99%

A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

Kok-Siang

Sulaiman

Reaz

et al. 2007

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 lm CMOS process and occupies an active area of 0.2 · 0.32 mm 2 . The CDR exhibits an RMS jitter of ± 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.

show abstract

“…These cores implement the lowest physical communication layer and have direct contact with the off-chip communication channel, whose materials and distances may vary widely. Specifications require these cores to consume low power while meeting tough BER requirements [9]. Such a tough trade-off has made the design of these cores very complicated.…”

Section: Introductionmentioning

confidence: 99%

Requirement-based design methods for adaptive communications links

Carballo

Nowka

Yoo

et al. 2004

Proceedings of the 41st Annual Design Automation Conference

View full text Add to dashboard Cite

High-speed communications link cores must consume low-power, feature low bit-error-rates (BER), and address many applications. We present a methodology to design adaptive link architectures, whereby the link's internal logic complexity, frequency, and supply are simultaneously adapted to application requirements. The requirement space is mapped to the design space using requirements measurement circuits and configurable logic blocks. CMOS results indicate that power savings of 60% versus the worst case are possible, while the area overhead is kept under 5%.

show abstract

An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications

Cited by 27 publications

References 4 publications

Design of high-speed clock and data recovery circuits

Design of high-speed clock and data recovery circuits

A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

Requirement-based design methods for adaptive communications links

Contact Info

Product

Resources

About