An 802.11g WLAN SoC

Abstract

The rapid adoption of the IEEE 802.11g wireless LAN (WLAN) standard has created a demand for low-cost, small-form-factor implementations. An integrated SoC that implements all of the functions of an 802.11g WLAN in a 0.18µm CMOS technology is presented in this paper. As shown in Fig. 5.2.1, the SoC consists of a 2.4GHz RF transceiver, analog baseband filters, data converters, digital physical layer (PHY), and media access controller (MAC). This IC essentially connects the RF antenna to the digital host computer. The one-chip solution reduces overall package cost and form factor. In addition, integration eliminates the area and power associated with driving package pins in a multi-chip implementation [1,2]. Furthermore, the merging of the analog and digital blocks on the same chip enables a wide digital-analog interface that allows for the use of sophisticated digital signal processing techniques to mitigate analog and RF impairments [2,3].Figure 5.2.2 shows the block diagram of the RF transceiver. A sliding-IF dual-conversion architecture is employed for both the receiver and transmitter. The RF local oscillator (LO RF ) frequency at 2/3 f RF (1.6GHz) and IF local oscillator (LO IF ) frequency at 1/3 f RF (0.8GHz) are generated from an integer-N synthesizer operating at 3.2GHz (twice the LO RF frequency). The voltage-controlled oscillator (VCO) is a varactor-tuned, inductively loaded LC tank. The choice of a VCO frequency at 2⋅LO RF reduces the size of the on-chip spiral inductor. The VCO output is divided by two and four to generate LO RF and LO IF . Inductive tuning is not used in the high-speed dividers because of the high f T available in the 0.18µm process. The loop filter is integrated on-chip using poly resistors and NMOS device capacitors. The synthesizer phase noise measured at the transmitter output, shown in Fig. 5.2.3, is -105dBc/Hz at 100kHz offset.The receiver in Fig. 5.2.2 converts the incoming RF signal to quadrature baseband outputs, while providing enough gain and interference rejection. The frequency allocation results in approximately 1.6GHz (2/3 f RF ) frequency separation between the incoming RF signal and the image channel. As a result, the bandpass elements used in the RF stages provide adequate image rejection, thereby eliminating the need for an explicit image rejection filter. The low-noise amplifier (LNA) consists of a cascoded differential pair with inductive degeneration and loading. The LNA has an adjustable RF gain to accommodate large RF input signals. In the low gain setting, 75% of the bias current is diverted from the output load to the supply, which results in a 12dB gain reduction. Figure 5.2.4 shows a circuit diagram of the dual down-conversion mixers. The RF mixer down-converts the 2.4GHz signal to an IF frequency of 800MHz. NMOS diode loads, which improve the IF gain stability over process and temperature, are used instead of bulky inductors. The NMOS loads are placed in deep N-wells to allow a source-to-bulk connection that removes transistor body effects. A common-mode f...

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