An 800MHz star-connected on-chip network for application to systems on a chip

Lee, Se-Joong; Song, Seong-Jun; Lee, Kangmin; Woo, Jeong-Ho; Kim, Sang Hoon; Nam, Byeong-Gyu; Yoo, Hoi‐Jun

doi:10.1109/isscc.2003.1234390

Cited by 36 publications

(2 citation statements)

References 5 publications

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“…The hierarchical topology is suitable for interconnecting homogeneous cores [ 20 ] with a low traffic hop distance—indicating the number of nodes needed to forward data to a target core [ 21 ]. The star topology offers a high-speed communication performance at low network traffic, characterized by short traffic hop distances [ 22 ]. Furthermore, it simplifies the process of adding and removing cores.…”

Section: Noc Topology For Rce-nn Acceleratormentioning

confidence: 99%

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

Kang,

Lee,

Jung

2024

Sensors

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Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part of modern life. For low-latency AI computation in IoT systems, there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) is a machine learning algorithm well-suited for implementation on edge devices due to its simple learning and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it is easy to adjust the network structure and learn additional data. Therefore, the RCE-NN can provide edge-based real-time processing for various sensor applications. However, previous RCE-NN accelerators have limited scalability when the number of neurons increases. In this paper, we propose a network-on-chip (NoC)-based RCE-NN accelerator and present the results of implementation on a field-programmable gate array (FPGA). NoC is an effective solution for managing massive interconnections. The proposed RCE-NN accelerator utilizes a hierarchical–star (H–star) topology, which efficiently handles a large number of neurons, along with routers specifically designed for the RCE-NN. These approaches result in only a slight decrease in the maximum operating frequency as the number of neurons increases. Consequently, the maximum operating frequency of the proposed RCE-NN accelerator with 512 neurons increased by 126.1% compared to a previous RCE-NN accelerator. This enhancement was verified with two datasets for gas and sign language recognition, achieving accelerations of up to 54.8% in learning time and up to 45.7% in recognition time. The NoC scheme of the proposed RCE-NN accelerator is an appropriate solution to ensure the scalability of the neural network while providing high-performance on-chip learning and recognition.

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Section: Noc Topology For Rce-nn Acceleratormentioning

confidence: 99%

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

Kang,

Lee,

Jung

2024

Sensors

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“…The advantages of employing a library-based approach to NoC design, where predesigned soft macros are appropriately instantiated and interconnected in order to form arbitrary topologies, are summarized in [43,44]. However, the full exploitation of customized network topologies requires an ad hoc design methodology spanning different levels of abstraction (ranging from application specification to physical implementation), in order to derive the most efficient NoC configuration for a given application domain.…”

Section: Topology Synthesismentioning

confidence: 99%

NoC Modeling and Topology Exploration

Tatas

Siozios

Soudris

et al. 2013

Designing 2D and 3D Network-on-Chip Architectures

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This chapter describes two of the most important tasks for designing NoC-based systems dealing with NoC modeling, as well as the topology exploration. For this purpose, state-of-the-art architectural solutions are discussed and open research topics are highlighted. Additionally, this chapter provides a description of alternative traffic models used as input to the NoC domain for evaluating the efficiency of various architectural parameters. The last topics discussed in this chapter are topology synthesis and application mapping onto the derived NoC architecture under various constraints. IntroductionWith the advent of chip multi-processors (CMP) and multi-core systems-on-chip (SoC), the network-on-chip (NoC) paradigm has been proposed as a viable solution to the problem of connecting the continuously increasing number of processing cores that are integrated on a single die. The communication problem is expected to become far more important with the demand for higher processing power posed by the majority of application domains and the technology scaling.Even though the NoC-based communication scheme introduces architectural scalability and performance enhancement, as already discussed in Chap. 1, however, careful design is absolutely required in order to achieve these gains. In this chapter, we discuss a number of architectural issues related to widely accepted NoC topologies. Additionally, the available academic and commercial solutions for topology modeling and synthesis are presented, whereas the main features/limitations for each of them are highlighted. In order to quantify the efficiency for each architectural selection, appropriate benchmarks are also required. For this purpose, throughout the second chapter we also introduce a number of typical traffic models employed for the scope of evaluating NoC architectures. Since the design, as well as the quantification of these NoC parameters are rather complex tasks, which cannot be easily performed without the usage of dedicated software tools, a number of frameworks are also introduced.K. Tatas et al., Designing 2D and 3D Network-on-Chip Architectures,

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Application Platform

2010

Mobile 3D Graphics SoC

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Two steps are encountered in any design process: "planning" and "making." Certain procedures are followed when we want to perform meaningful tasks towards building a target structure. As the target structure takes on more complexity, well-established design procedures are essential. This applies in SoC design, which is strongly driven by its target applications such as multimedia and mobile communications. SoC engineers have to consider factors like quality, cost and delivery (QCD). In that sense, their design procedures naturally seek the reuse of previously developed techniques and materials at every possible design step.In a popular English dictionary, a "system" is defined as a set and a way of working in a fixed plan with networks of components. In addition to this, SoC requires one more idea, which is the integration of components on a single semiconductor chip. So it follows that we need to focus on two concepts: the fixed plan, and integration. We can catch the concept of predetermined architecture from the fixed plan; and integration involves the network and component-based design. Considering that modern digital gadgets require not only hardware (HW) components but also software (SW) programs, we can begin to see what the "platform" means in SoC design.The platform is a set of standalone modules that become the basis of the system. These standalone modules are pre-integrated and combine HW and SW componentswe call them the "reference architectures." They are also well-verified and have welldefined external interfaces. The platform guides what designers do, and this guidance determines the design flow. The platform concept helps us to design a more complicated and less buggy system within limited QCD factors by reusing and upgrading prebuilt HW and SW components.

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An 800MHz star-connected on-chip network for application to systems on a chip

Cited by 36 publications

References 5 publications

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

NoC Modeling and Topology Exploration

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