An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

Seki,; Kume,; Ohji,; Tanaka, M.; Adachi,; Ushiyama,; Shimohigashi,; Wada, Yasuhiro; Komori,; Nishimoto,; Izawa,; Hagiwara,; Kubota,; Shohji,; Miyamoto,; Saeki,; Ogawa, Takumi

doi:10.1109/isscc.1990.110129

Cited by 2 publications

(1 citation statement)

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“…One approach is to iterate the erase and verify sequence [4]- [6]. In this approach, to obtain the tight distribution of threshold voltage, pre-program for all bytes is carried out, and the gradual erase and verify sequence will be iterated until the threshold voltages for all bytes in the array are less than or equal to the desired value.…”

Section: Introductionmentioning

confidence: 99%

A self-convergence erasing scheme for a simple stacked gate flash EEPROM

Yamada

Suzuki²,

Obi³

et al.

International Electron Devices Meeting 1991 [Technical Digest]

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A new erasing method for a simple stacked gate Flash EEPROMs is described. The method makes use of avalanche hot carrier injection after erasure by Fowler-Nordheimv-N) tunneling. The threshold voltages converge to a certain "steady-state" as a result of the injection. The steady-state is caused by a balance between the avalanche hot electron injection into the floating gate and the avalanche hot hole injection into the floating gate, and can be controlled easily by the channel doping. Tight distribution of threshold voltages and stable erasure without over-erased cells are demonstrated by applying cells using 0.6pm CMOS technology. In addition, short erase time is realized using the new erase sequence.

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Section: Introductionmentioning

confidence: 99%

A self-convergence erasing scheme for a simple stacked gate flash EEPROM

Yamada

Suzuki²,

Obi³

et al.

International Electron Devices Meeting 1991 [Technical Digest]

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Selective erasable and programmable NAND‐type MNOS memory

Sato

Uéda

Kojima

et al. 1992

Electron Comm Jpn Pt II

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This study was made of a new programming method and memory characteristics of an NAND‐type MNOS memory cell which uses half the size of the conventional two‐transistor structure using the same design rule. As a result, it was found that inadvertent writing can be prevented under the write inhibit mode by using a new sequencing (PURGE mode) which moves unnecessary thermal electrons generated under MNOS gate to the bit lines. Also, it was verified that selective rewriting by NAND type can be realized. This prototype of NAND‐type MNOS memory cell can realize PURGE effect by applying 3 V and a very short pulse of 30 ns. It was found out also that possible number of PURGES of unselected memory cells at each writing is about 1010. The limit of the read cycle is about 106 when the word line consists of 128 bytes.

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An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

Cited by 2 publications

References 0 publications

A self-convergence erasing scheme for a simple stacked gate flash EEPROM

A self-convergence erasing scheme for a simple stacked gate flash EEPROM

Selective erasable and programmable NAND‐type MNOS memory

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