An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

Ramadurai, Vinod; Pilo, H.; Andersen, J.; Braceras, G.; Gabric, J.; Geise, D.; Lamphier, S.; Tan, Yue

doi:10.1109/jssc.2008.2006433

Cited by 11 publications

(8 citation statements)

References 5 publications

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“…2 (b). The novel design uses differential voltage amplifier instead of latch-type sense amplifier [4] because the former one is able to operate before global bitline has voltage differences, while latch-type need to wait for certain voltage difference of global bitlines (like 100 mV) and accurate open timing, which is hard to be precise since the long distance timing and would therefore increase access time. The positive input of the left amplifier is connected to the negative input of the right one and vice versa.…”

Section: Proposed Two-stage Sensing Schemementioning

confidence: 99%

A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique

Zheng

Liu

Chen

et al. 2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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This paper focuses on high speed embedded SRAM design, especially on novel circuit technique to improve SRAM access time. A new two-stage sensing scheme which is able to reduce long interconnection metal line delay by transferring differential signals with half swing amplitude has been proposed. Post-layout simulation results show that the long distance signal transmission time has been decreased by 45%. Chip measurement shows the access time has been decreased by 23% at the expense of little area penalty (1.3%) and some read power penalty (about 16%) mainly caused by 2nd-stage sense amplifiers.

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Section: Proposed Two-stage Sensing Schemementioning

confidence: 99%

A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique

Zheng

Liu

Chen

et al. 2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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“…Decoupling capacitors are placed near noise aggressors (such as embedded CAMS) and also around sensitive circuits such as PLLs. These DT decaps have also been used to form unique power-saving circuit structures [7].…”

Section: Understanding Soi Effects In a Design Systemmentioning

confidence: 99%

An SOI technology optimized ASIC design system

Zuchowski¹,

Bentlage²,

Kuemerle³

2010

2010 IEEE International SOI Conference (SOI)

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Silicon on insulator (SOI) technology is an excellent choice for chip designs that require high performance and low power. IBM's SOI custom logic (ASIC) design system uses internal tools and flows in combination with solutions from a network of proven EDA vendors to support these high performance designs while managing the additional complexities introduced by the SOI process. The use of a qualified design system can add schedule predictability while simultaneously achieving high performance and power predictability.In this paper, we describe a high performance methodology for custom designs using a combination of Cadence, Synopsys, and IBM tools and flows. We discuss the benefits and challenges of the SOI technology and share results of high performance designs that were successfully manufactured using this methodology.Index Terms -very-large-scale integration, application specific integrated circuits, silicon on insulator, power, custom logic, design system.

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“…At present, voltage-mode SAs are widely used because of simplicity and robustness [5][6][7][8][9][10][11], most of which are based on cross-coupled invertors. The delay of SAs is small because of positive feedback of cross-coupled invertors while enough voltage difference between a pair of bit lines is required due to the offset of voltage-mode SAs.…”

Section: Introductionmentioning

confidence: 99%

“…The small bit cell must drive large capacitive bit lines resulting in large delay. In order to overcome the problem, decreasing the capacitance of bit lines may be used by divided bit lines and two-level sensing technique [5,12]. The local bit line connects fewer bit cells, resulting in low bit line discharge delay, but large energy is consumed because of full voltage swing on the bit lines.…”

Section: Introductionmentioning

confidence: 99%

Review of Sense Amplifiers for Static Random Access Memory

Zhu¹,

Bai²,

Wu³

2013

IETE Tech Rev

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Sense amplifier (SA) is being viewed as one of the most critical circuits in the periphery of high-speed, low-power-embedded static random access memory (SRAMs). This paper provides a systematic overview of voltage-mode, charge-transfer, current-mode SAs, and calibration-based SAs for SRAM. Recent advances in developing SAs have paved the way for lower delay, lower energy, and higher reliability. For comparison, all SAs based on 65 nm CMOS technology are simulated under different power supplies, bit-line capacitances, and various process corners. When the bit-line capacitance is 50 fF, charge-transfer and current-mode SAs are about 40% faster than voltage-mode SAs, and the energy consumption of charge-transfer SA is 30% lower than that of other voltage-mode SAs. Delay and energy of HCI-trimming SA and multi-sized SA are about equal to that of voltage-mode SAs. Because of low bit-line precharged voltage, the energy of charge-limited sequential SA (CLSSA) is 64% lower than that of charge-transfer SA, while the delay of CLSSA is five times larger than the other SAs. AUTHORSJiafeng Zhu received the M.S. degree from Southeast University, China, in 2010 in electronic engineering. He is currently a Ph.D. candidate in National ASIC System Engineering Research Center, Southeast University, China. His research interests include high performance and low power SRAM design and mix-signal IC design.

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An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

Cited by 11 publications

References 5 publications

A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique

A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique

An SOI technology optimized ASIC design system

Review of Sense Amplifiers for Static Random Access Memory

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