An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130 nm CMOS

Tavernier, Filip; Bonacini, S.; Moreira, P.

doi:10.1088/1748-0221/7/12/c12022

Cited by 5 publications

(4 citation statements)

References 2 publications

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“…The purpose of the Programmable Delay block is to be able to skew the input signals to the local clock phase and adjust the ART stream to it. To perform that, the ASIC uses four copies of the 8-channel Phase Aligner core developed at CERN [78].…”

Section: Art -Micromegas Trigger Data Aggregator and Serializer Asicmentioning

confidence: 99%

The New Small Wheel electronics

et al. 2023

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The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that don't originate from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the “small” Thin Gap Chambers, with a total of 2.45 million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm2 at the expected HL-LHC luminosity of ℒ = 7.5 × 1034 cm-2 s-1. The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.

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Section: Art -Micromegas Trigger Data Aggregator and Serializer Asicmentioning

confidence: 99%

The New Small Wheel electronics

et al. 2023

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“…The L1DDC is the interface between multiple FE boards and the FELIX network interface. This is achieved using the high-speed serializer/deserializer GigaBit TransceiverX (GBTX) ASIC [9] developed at CERN. The GBTX is a radiation-tolerant ASIC fabricated using the IBM/GlobalFoundries 130 nm CMOS technology.…”

Section: Electronicsmentioning

confidence: 99%

Electronics performance of the ATLAS New Small Wheel Micromegas wedges at CERN

Tzanis¹

2020

J. Inst.

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A series of upgrades are planned for the LHC accelerator to increase its instantaneous luminosity to 7.5 × 1034 cm−2s−1. The luminosity increase drastically impacts the ATLAS trigger and readout data rates. The present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector which is expected to be installed in the ATLAS underground cavern by the end of the Long Shutdown 2 of the LHC . With the final micromegas (MM) quadruplets (modules) already produced the activities concerning the integration of the modules into the final, fully equipped MM wedges, that will then be installed on the wheel structure on surface, are currently in full swing at CERN. One crucial part of the integration procedure concerns the installation, testing and validation of the on-detector electronics and readout chain for a very large system with more than 2.1 millions electronic channels in total. These include ∼4 thousands MM Front-End Boards (MMFE8), custom printed circuit boards each one housing eight 64-channel VMM Application Specific Integrated Circuits (ASICs) that interface with the ATLAS Trigger and Data Acquisition (TDAQ) system through ∼1 thousands data-driver cards (ADDC & L1DDC, respectively). The readout chain is based on optical link technology (GigaBit Transceiver links) connecting the back-end to the front-end electronics via the Front-End LInk eXchange (FELIX), a newly developed system that will serve as the next generation readout driver for ATLAS. Experience and performance results from the first large-scale electronics integration tests performed at CERN on final MM wedges, including system validation with cosmic-rays, are presented.

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“…An illustration of the implementation is shown in Fig. 4 (a), in which two 4-step phase shift cells are utilized and the output clock is selected via another control bit d [4].…”

Section: B Phase-shift In the Pad Tdsmentioning

confidence: 99%

“…A variety of techniques are available for delay compensation. Conventionally, either a delay component from digital cell library or a custom delay circuit with feedback control can be utilized for delay generation [4]. The former relies on sole cell delay and is subject to temperature, supply voltage and process variations, whereas the latter is stabilized with a feedback loop but is complicated in realization and consumes relatively larger silicon area and power, particularly when triple modular redundancy (TMR) is needed to mitigate single-event effect (SEE).…”

Section: Introductionmentioning

confidence: 99%

A programmable time alignment scheme for detector signals from the upgraded muon spectrometer at the ATLAS experiment

Wang

Guan

Chapman

et al. 2017

Nuclear Instruments and Methods in Physics Research Section A:

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Abstract-We present a programmable time alignment scheme used in an ASIC for the ATLAS forward muon trigger development. The scheme utilizes regenerated clocks with programmable phases to compensate for the timing offsets introduced by different detector trace lengths. Each ASIC used in the design has 104 input channels with delay compensation circuitry providing steps of ~ 3 ns and a full range of 25 ns for each channel. Detailed implementation of the scheme including majority logic to suppress single-event effects is presented. The scheme is flexible and fully synthesizable. The approach is adaptable to other applications with similar phase shifting requirements. In addition, the design is resource efficient and is suitable for cost-effective digital implementation with a large number of channels.

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An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130 nm CMOS

Cited by 5 publications

References 2 publications

The New Small Wheel electronics

The New Small Wheel electronics

Electronics performance of the ATLAS New Small Wheel Micromegas wedges at CERN

A programmable time alignment scheme for detector signals from the upgraded muon spectrometer at the ATLAS experiment

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