Electronics performance of the ATLAS New Small Wheel Micromegas wedges at CERN

Abstract

A series of upgrades are planned for the LHC accelerator to increase its instantaneous luminosity to 7.5 × 1034 cm−2s−1. The luminosity increase drastically impacts the ATLAS trigger and readout data rates. The present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector which is expected to be installed in the ATLAS underground cavern by the end of the Long Shutdown 2 of the LHC . With the final micromegas (MM) quadruplets (modules) already produced the activities concerning the integration of the modules into the final, fully equipped MM wedges, that will then be installed on the wheel structure on surface, are currently in full swing at CERN. One crucial part of the integration procedure concerns the installation, testing and validation of the on-detector electronics and readout chain for a very large system with more than 2.1 millions electronic channels in total. These include ∼4 thousands MM Front-End Boards (MMFE8), custom printed circuit boards each one housing eight 64-channel VMM Application Specific Integrated Circuits (ASICs) that interface with the ATLAS Trigger and Data Acquisition (TDAQ) system through ∼1 thousands data-driver cards (ADDC & L1DDC, respectively). The readout chain is based on optical link technology (GigaBit Transceiver links) connecting the back-end to the front-end electronics via the Front-End LInk eXchange (FELIX), a newly developed system that will serve as the next generation readout driver for ATLAS. Experience and performance results from the first large-scale electronics integration tests performed at CERN on final MM wedges, including system validation with cosmic-rays, are presented.

The Control System of the New Small Wheel Electronics for the ATLAS experiment

“…The Control System of the New Small Wheel Electronics for the ATLAS experiment physics experiments, it provides various user-configurable interfaces, such as SPI, I2C or JTAG, and is capable of performing simultaneous operations. In this SCA-GBTx-FELIX communication chain [3], the last two components can be viewed as data mediators, so there is one piece missing: the back end logic that actually builds the packets-to-be-transmitted to the SCA, and handles the inbound traffic from the ASIC. This is a software suite, which is a dedicated Open Communications Platform Unified Automation (OPC UA) server [7].…”

The Detector Control System of the New Small Wheel Electronics for the ATLAS experiment

“…A graphic representation of the NSW sector (left) which consists of 8 layers of Micromegas in the inner part and sandwiched by 4+4 layers of sTGC detectors in the outer parts and view of the NSW (right) with 16 sectors in total. [10] host TDS chips. The ROC aggregates L1 data from many VMMs [4] and sends them to (Front End LInk eXchange (FELIX) [5] via the GBTx [6].…”

“…Overview of the NSW electronics scheme. The front-end detector boards are depicted on the left (for MM and sTGC), the data-driver cards (L1DDC, ADDC) in the middle while the back-end electronics can be seen on the right [10].…”

Development of the Configuration, Calibration and Monitoring System of the New Small Wheel Electronics for the ATLAS experiment

“…In order to meet the requirements of different front-end ASICs used in high-energy physics experiments, it provides various user-configurable interfaces, such as SPI, I2C or JTAG, and is capable of performing simultaneous operations. In this SCA-GBTx-FELIX communication chain [8], the last two components can be viewed as data mediators, so there is one piece missing: the back end logic that actually builds the packets-to-be-transmitted to the SCA, and handles inbound traffic from the ASIC. This is a software suite, which is a dedicated Open Communications Platform Unified Automation (OPC UA) server.…”

“…Figure 2:Overview of the on/off-detector electronics and the DCS, Configuration and Calibration path via the SCA, the FELIX and the SCA OPC UA Server. A common readout path and a separate trigger path are developed for each detector technology [8]. …”