An 8-bit current-steering digital to analog converter

Yi, Shu-Chung

doi:10.1016/j.aeue.2011.10.003

Cited by 19 publications

(4 citation statements)

References 7 publications

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“…A 5‐bit binary weighted current mode DAC is used to generate desired stimulation current. In this structure, one bit in the digital input directly turns a relative current source on or off 72 . The amplitude of the stimulation current can be changed according to digital code receiving from the external control unit.…”

Section: Circuit Designmentioning

confidence: 99%

“…In this structure, one bit in the digital input directly turns a relative current source on or off. 72 The amplitude of the stimulation current can be changed according to digital code receiving from the external control unit. Figure 4 shows the schematic of the DAC in which the maximum currents (I DAC ) are 31 and 248 μA based on I GC1 and I GC2 values, respectively.…”

Section: Dacmentioning

confidence: 99%

See 1 more Smart Citation

A 2‐mA charge‐balanced neurostimulator in 0.18‐μm/1.8 V standard CMOS process

Hosseinnejad

Katebi

Erfanian

et al. 2022

Circuit Theory & Apps

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This paper presents a programmable neurostimulator 4 Â V DD with 7.2 V operating voltage in a 0.18-μm/1.8 V CMOS process. The output voltage compliance exceeds 6.2 V. A current gain control is designed to adjust bias current.A 5-bit current mode digital-to-analog converter (DAC) is used to set delivered current in current driver. A high output impedance current mirror is designed to guarantee charge balancing. The charge mismatch after biphasic stimulation is about 0.14%. Moreover, current mirrors are turned off after stimulation to decrease power consumption. The headroom voltage is about 1 V for all the voltage drivers and the current mirrors. The proposed neurostimulator occupies 0.95 Â 0.95 mm 2 with a maximum current range of 0-2000 μA and a power consumption less than 60 μW.

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Section: Circuit Designmentioning

confidence: 99%

Section: Dacmentioning

confidence: 99%

A 2‐mA charge‐balanced neurostimulator in 0.18‐μm/1.8 V standard CMOS process

Hosseinnejad

Katebi

Erfanian

et al. 2022

Circuit Theory & Apps

View full text Add to dashboard Cite

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“…Digital-to-analog converters (DACs) play a significant role in diverse applications such as audio, video (Esmaili and Babazadeh, 2019a) and wireless communication (Wang et al , 2018) due to its function; interfacing digital signal processing device and outside world. Recently, DACs with low power consumption and small die area have become a topic of interest especially in portable devices (Yi, 2012; Sharifi et al , 2016). Small size DAC is very important for ADC built-in self-test (Chen et al , 2020).…”

Section: Introductionmentioning

confidence: 99%

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

Idros

Rosli

Aziz

et al. 2021

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Purpose The purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures. Design/methodology/approach The conventional DAC topology performance tends to degrade at high-resolution applications. A hybrid topology, which combines an equal number of bits of thermometer coding and binary-weighted resistor architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V. Findings Measured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input range of 0.9 V at the clock rate of 200 MHz, and this DAC was proven monotonic. This 0.068 mm2 DAC consumed 12.6 mW for the data conversion. Originality/value This paper is of value in showing the equal division of bits from thermometer coding and binary-weighted resistor architectures provides smaller die size and enhances the performance of hybrid DAC, in terms of linearity, which are DNL and INL errors and guarantees monotonicity at higher sampling frequency.

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“…Figure 1. Single ended DAC construction [9] Ring oscillators can be developed in any standard CMOS process and might need fewer chip area. The design is forthright and ring architectures can be used to offer multiple output phases and wide tuning ranges.…”

mentioning

confidence: 99%

Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)

Rahman

Mohamed

Reaz³

et al. 2014

ijeei

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A low power 6-bit CMOS ring based digitally controlled oscillator (DCO) design is presented. The design is proposed based on binary-to-thermometer (BT) decoder current mirror digital-to-analog converter (DAC) and ring-based voltage controlled oscillator (VCO). The DCO is implemented using 0.18 µm CEDEC Mentor Graphic CMOS process at 2.0 V supply voltage. The simulation results show that the proposed DCO consumed only 9.5764 mW of power besides the output voltage is 1.8121 V and local oscillator clock frequency is 33 MHz. The phase noise parameter is-132 dBc/Hz with an offset frequency of 100 kHz has also been reported for the proposed circuits.

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An 8-bit current-steering digital to analog converter

Cited by 19 publications

References 7 publications

A 2‐mA charge‐balanced neurostimulator in 0.18‐μm/1.8 V standard CMOS process

A 2‐mA charge‐balanced neurostimulator in 0.18‐μm/1.8 V standard CMOS process

A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm

Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)

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