An 8-bit 2-V 2-mW 0.25-mm/sup 2/ CMOS DAC

Wang, Huei-Chi; Kao, Hong-Sing; Lee, Tai-Cheng

doi:10.1109/apasic.2004.1349418

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…In high speed DAC testing the skew between the data bits requires accurate control, therefore to use a high speed Word Generator instead of FPGA is recommended. Table 2 puts together some previously reported CMOS 8 bits DAC with similar performance [8,9]. Although the comparative study is difficult because tecnology and power supply are not the same, it is possible conclude that the design strategy here presented is more efficient regarding area and power consumption without a significant overhead in SFDR, INL, DNL and sampling frequency specifications.…”

Section: Resultsmentioning

confidence: 87%

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter

Hernández¹,

Noije²,

Roa

et al. 2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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This paper presents a small area CMOS current-steering segmented digital-to-analog converter (DAC) design used in a RF transmitter stage for 2.45GHz Bluetooth applications. The current source design strategy is based on an iterative scheme which variables are adjusted by a simple way, satisfying the requirements, minimizing power consumption and reaching the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy of small area consumption for the current-steering DAC design is included. The DAC was designed and implemented in 0.35µm 4M2P CMOS technolyogy. Some performance results obtained through experimental test are: chip active area of only 200µm × 200µm, full scale output current of 700µA at 3.3V power supply, INL=0.3LSB, DNL=0.37LSB, SFDR=58dB for output sine wave frequency of F out = 1MHz and F s = 50MHz sampling frequency, SFDR=52dB for F out = 1MHz and F s = 10MHz.

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Section: Resultsmentioning

confidence: 87%

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter

Hernández¹,

Noije²,

Roa

et al. 2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

View full text Add to dashboard Cite

show abstract

A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter

Hernández

Noije

Roa

et al. 2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper presents a small-area CMOS current-steering segmented digital-to-analog converter (DAC) design intended for RF transmitters in 2.45 GHz Bluetooth applications. The current-source design strategy is based on an iterative scheme whose variables are adjusted in a simple way, minimizing the area and the power consumption, and meeting the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy to attain a small-area current-steering DAC are included. The DAC was designed and implemented in 0.35 lm CMOS technology, requiring an active area of just 200 lm 9 200 lm. Experimental results, with a full-scale output current of 700 lA and a 3.3 V power supply, showed a spurious-free dynamic range of 58 dB for a 1 MHz output sine wave and sampling frequency of 50 MHz, with differential and integral nonlinearity of 0.3 and 0.37 LSB, respectively.

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An 8-bit 2-V 2-mW 0.25-mm/sup 2/ CMOS DAC

Cited by 2 publications

References 9 publications

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter

A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter

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