An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer

Lee, Dong-Myung; Han, Jaehong; Han, Gunhee; Park, Sung Min

doi:10.1109/jssc.2010.2077050

Cited by 88 publications

(27 citation statements)

References 16 publications

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“…To improve the bandwidth of CMOS PDs, spatially-modulated PDs (SMPDs) have been reported [3,4]. SMPDs employ differential, symmetrical structure through the difference between currents I light and I dark to eliminate slow diffusion current generated in the substrate.…”

Section: Introductionmentioning

confidence: 99%

A compact, low-power-consumption 5-Gbps OEIC receiver without equalizer fabricated in 0.18-µm CMOS technology

Chen

Wang

2017

IEICE Electron. Express

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A low-cost, compact 5-Gbps fully integrated CMOS optical receiver without equalizer is fabricated in this paper in a standard 0.18-µm CMOS technology. The measured responsivity of the DNW-strip-SMPD operating in avalanche mode is 1.4 A/W, while the bandwidth is 2.9 GHz with 11.6 V reverse bias voltage. The application for 5-Gbps very-short-reach optoelectronic integrated circuit (OEIC) receiver with a bit-error rate <10 −12 at incident optical power of −4 dBm has been experimentally demonstrated. The core chip area of the OEIC receiver is 0.736 mm by 0.515 mm, and it consumes 96 mW from the 1.8 V supply. Our OEIC receiver has the smallest area and the lowest power consumption in the OEIC receivers reported so far fabricated in 0.18-µm CMOS technology.

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Section: Introductionmentioning

confidence: 99%

A compact, low-power-consumption 5-Gbps OEIC receiver without equalizer fabricated in 0.18-µm CMOS technology

Chen

Wang

2017

IEICE Electron. Express

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“…As one of these, low-cost 850-nm optical interconnects based on vertical-cavity surface-emitting lasers and multimode fibers are finding increasing ranges of applications such as home networks [6], communications in vehicles and airplanes [7], rack-to-rack interconnects within data centers and computer clusters [8], [9], and onboard interconnects [8][9][10][11][12][13]. 850-nm optical receivers that include monolithically integrated silicon photodetectors (PDs) and complementary metal-oxide-semiconductor (CMOS) electronics are particularly attractive since they have great cost benefits provided by CMOS technology as well as improved performance due to elimination of parasitic pad capacitances and bonding wire inductances that are unavoidable in hybrid approaches [14][15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

“…Several integrated optical receivers based on standard CMOS technology (CMOS-Rxs) have been reported [14][15][16][17][18][19][20][21]. The most critical issue for realizing high-performance CMOSRxs is development of high-performance CMOS-compatible silicon photodetectors (CMOSPDs).…”

Section: Introductionmentioning

confidence: 99%

A fully-integrated 125-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

Lee¹,

Youn²,

Park³

et al. 2014

Opt. Express

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We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxidesemiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOScompatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

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“…However, this design method has high power consumption due to the several TIAs deployed. In conventional Rx circuits, the TIA may not have enough gain and bandwidth to drive other circuits and as a result, may require the use of LA, equalizer [10][11], and other performance enhancement circuitry. However, due to the need for high data-rate and high performance operation, the need for the additional circuitry (LA, equalizer, etc.)…”

Section: Introductionmentioning

confidence: 99%

Design of small-area transimpedance optical receiver module for optical interconnects

Sangirov

Ukaegbu

Nguyen

et al. 2014

16th International Conference on Advanced Communication Technology

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Abstract-The development and miniaturization of electronic devices and components is pushing the system devices and their interconnecting interfaces to become even smaller. Thus, reducing the size of receiver (Rx) and transmitter (Tx) chips plays an plays an important role in designing a small-size optical modules utilized in o/e and e/o converters. Therefore, designing a small-area optical Rx may require intuitive solutions, such as building single-ended Rx and utilizing some of the advantages of differential Rx. Optical Rx should convert optical input signal to voltage output signal and provide sufficient gain and frequency operation for feeding to subsequent blocks including clock and data recovery circuit (CDR) and/or Serializer and Deserializer (SerDes). Therefore, we have designed a small-area transimpedance optical receiver (TIORx) using regulated-cascode (RGC) as an input stage which converts input photocurrent to voltage signal. The RGC block is connected to post amplifying stages to increase the overall transimpedance gain of the TIORx. The post amplifying gain stages utilizes two intersecting active feedback in order to increase the frequency operation in addition to increasing the gain of the proposed TIORx chip. The TIORx module is designed in a 0.13μm CMOS technology and works up to 10 Gbps data rate. The TIORx chip core occupies an area of 0.051mm 2 with power consumption of 16.9 mW at 1.3 V. A measured 3-dB bandwidth of 6.9 GHz was obtained for the TIORx module with a transimpedance gain of 60 dBΩ.

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An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer

Cited by 88 publications

References 16 publications

A compact, low-power-consumption 5-Gbps OEIC receiver without equalizer fabricated in 0.18-µm CMOS technology

A compact, low-power-consumption 5-Gbps OEIC receiver without equalizer fabricated in 0.18-µm CMOS technology

A fully-integrated 125-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

Design of small-area transimpedance optical receiver module for optical interconnects

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