An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

Mizuno, Hiroyuki; Ishibashi, K.; Shimura, T.; Hattori, Toshihiro; Narita, Susumu; Shiozawa, Kenji; Ikeda, Shuji; Uchiyama, Kunio

doi:10.1109/4.799853

Cited by 71 publications

(17 citation statements)

References 11 publications

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“…c) Dynamic threshold voltage SRAM: Dynamic SRAM (DTSRAM) architecture can be used to reduce leakage energy dissipation in memory structures. Using body biasing, the subthreshold leakage can be reduced without sacrificing data stability [81]. In a time-based dynamic scheme, high is assigned to the cache lines which are not accessed for a certain period (30 s-100 s), and a low is assigned to the cache lines which are in frequent use to maintain high performance [82].…”

Section: ) Leakagementioning

confidence: 99%

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

2003

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Section: ) Leakagementioning

confidence: 99%

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

2003

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“…Threshold voltage can also be scaled by applying a back-body bias to the silicon substrate and wells. Both Intel and Hitachi have successfully demonstrated adaptive body biasing for low-power and highperformance processors [5,8]. This work shows that by dynamically scaling threshold voltage, leakage current savings of up to 25× can be achieved.…”

Section: Low-leakage Techniquesmentioning

confidence: 89%

Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations

Hempstead

Wei

Brooks

2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Unlike traditional performance oriented applications, sensor network nodes are primarily constrained by operation lifetime, which is limited by power consumption. Advanced CMOS process technologies provide ever increasing transistor density and improved performance characteristics. However, shrinking feature size and decreasing threshold voltages also lead to significant increases in leakage current, which is especially troublesome for applications with significant idle times.This work investigates tradeoffs between leakage and active power for low-throughput applications. We study these issues across a range of process technologies on a computing architecture that provides explicit support for fine-grain leakage-control techniques such as Vdd-gating and adaptive body bias. We present a methodology for selecting design parameters, including choice of process technology, that makes the optimal tradeoff between active power and leakage power for a given workload. Our results show that leakage power will dominate the selection of process technology, and architectures that support advanced leakage control techniques at the circuit level will be essential. We argue that without advanced lowpower architectures future nano-scale process technologies will not be suited for sensor network applications.

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“…However, having a quasi-floating. VBB at each MOST induces instabilities such as history effects, as in SOl, resulting in intra-die fluctuations in VT [24]. This is especially so for high-speed LSls.…”

Section: Peripheral Logic Circuitsmentioning

confidence: 99%

Low-Voltage Embedded-RAM Technology: Present and Future

Itoh

Mizuno

2002

IFIP Advances in Information and Communication Technology

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Abstract:First, key issues for low-voltage «IV) embedded RAMs are summarized in terms of stable operation, suppression of leakage (gate-tunneling/subthreshold) currents, and speed variation of memory cells and peripheral logic circuits. Next, DRAM and SRAM cells to cope with the above issues, the circuit design focusing on subthreshold-current issue, and suppression of or compensation for design-parameter variations to reduce the speed variations are discussed. Voltage converters and power management for low-power and low-voltage operation are also explained. Finally, based on the above discussions, a perspective is given with emphasis on needs for simple/high signal-to-noise ratio memory cells (such as gain cells) with a pure logic compatible process, high-speed subthreshold-current reduction focusing on active mode, and memory-rich SoC architectures.

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An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

Cited by 71 publications

References 11 publications

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations

Low-Voltage Embedded-RAM Technology: Present and Future

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