An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals

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This chapter starts with a brief introduction of the analog-to-digital conversion process in Sect. 2.1 and a discussion of factors that define the performance of ADCs in Sect. 2.2. ADC performance limitations and trends are addressed in Sect. 2.3. In Sect. 2.4, a brief discussion of popular Nyquist-rate ADC topologies is given where the topologies most relevant to the focus of this book are discussed with the associated tradeoffs. A signal/system-aware design approach which exploits certain signal properties to enhance the ADC performance is discussed in Sect. 2.5 and examples are shown. Introduction to Analog-to-Digital ConvertersAn analog-to-digital converter is an electronic circuit which converts a continuoustime and continuous-amplitude analog signal to a discrete-time and discreteamplitude signal [1]. The analog-to-digital conversion involves three functions, namely sampling, quantizing and encoding [2], as shown in Fig. 2.1. After the conversion, the continuous quantities have been transformed into discrete quantities with a certain amount of error due to the finite resolution of the ADC and imperfections of electronic components. The purpose of the conversion is to enable digital processing on the digitized signal.ADCs are essential building blocks in electronic systems where analog signals have to be processed, stored, or transported in digital form. The ADC can be a stand-alone general purpose IC, or a subsystem embedded in a complex system-onchip (SoC) IC. A main driving force behind the development of ADCs over the years has been the field of digital communications due to continuous demand of higher data rates and lower cost [2]. In Fig. 2.2, a block diagram of a typical digital communication system is shown and the location of the ADC in the system is indicated [3]. The ADC is normally preceded by signal conditioning blocks (e.g. amplifiers, filters, mixers, modulators/demodulators, detectors, etc.) and followed by the baseband digital signal processing unit. With the advance in CMOS process

Section: Exploiting Signal Propertiesmentioning

confidence: 99%

Enhancing ADC Performance by Exploiting Signal Properties

et al. 2015

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“…Secondly, the driver of the parallel-sampling ADC has to deliver a larger output signal swing which can be a limitation of this architecture. However, the reduction of the sampling capacitor makes the ADC easier to drive and doesn't affect the overall power efficiency [15,22,33] and the required large output signal swing of the ADC driver can be achieved by using the mixed-supply-voltage approach without compromising the speed as proposed in [26,27].…”

Section: Sncdr [Db] Optimal Power Back-off [Db]mentioning

confidence: 99%

Parallel-Sampling ADC Architecture for Multi-carrier Signals

et al. 2015

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This chapter starts with a brief introduction of broadband multi-carrier transmission in Sect. 3.1. Section 3.2 describes the amplitude properties of multicarrier signals, especially their large peak-to-average ratio. A discussion of the ADC dynamic range requirement for a multi-carrier system is given in Sect. 3.3. Section 3.4 reviews power reduction techniques to enhance the SNR of noise limited ADCs in advanced CMOS technologies. Section 3.5 presents a parallelsampling architecture for ADCs to convert multi-carrier signals efficiently by exploiting their amplitude statistical properties. ADCs with this architecture are able to have a larger input signal range without causing excessive distortion while showing an improved accuracy over the small amplitudes that have much higher probability of occurrence due to the multi-carrier signal amplitude properties. The power consumption and area of ADCs with the parallel-sampling architecture can be reduced to achieve a desired SNR for multi-carrier signals compared to conventional ADCs. Section 3.6 proposes four implementation options of the parallelsampling ADC architecture and Sect. 3.7 concludes the chapter.

“…This section describes the architecture and circuit design of a 200 MS/s 12-b switched-capacitor pipeline ADC with a parallel-sampling first stage [1]. The proposed parallel-sampling first stage can be applied to pipeline ADCs with different accuracy and speed specifications for multi-carrier signals.…”

Section: Parallel-sampling Architecture Applied To a Pipeline Adcmentioning

confidence: 99%

Implementations of the Parallel-Sampling ADC Architecture

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This chapter describes circuit implementations of the parallel-sampling ADC architecture presented in Chap. 3. The parallel-sampling architecture is applied to two ADC architectures (a pipeline and a time-interleaving SAR ADC architecture), which are suitable for designing high-speed and medium-to-high resolution ADCs, to improve the ADC power efficiency for multi-carrier signals. Section 4.1 describes the architecture and operation of a 200 MS/s 12-b switchedcapacitor pipeline ADC with a parallel-sampling first stage, which is suitable for broadband multi-carrier receivers for wireless standards such as LTE-advanced and the emerging generation of Wi-Fi (IEEE802.11ac) . A circuit implementation of the parallel-sampling first stage of the pipeline ADC is presented and simulation results are given. Section 4.2 presents the architecture and operation of a 4 GS/s 11 b timeinterleaved ADC with a parallel-sampling frontend stage, which targets wideband direct sampling receivers for DOCSIS 3.0 cable modems . Circuit implementation and simulation of the 4 GS/s parallel-sampling frontend stage are given. Due to the complexity of implementing the proposed 4 GS/s ADC on chip, a two-step design approach was adopted. In Sect. 4.3, a prototype IC of an 11 b 1 GS/s ADC with a parallel sampling architecture is presented, which serves as a first step to validate the parallel-sampling ADC concept and the performance of the high-speed parallelsampling frontend and detection circuits. In future work, the frontend stage of the IC can be interleaved by four times to achieve the aggregate sample rate of 4 GHz of the proposed ADC discussed in Sect. 4.2. Conclusions of this chapter are drawn in Sect. 4.4.