An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC

Cao, Yuefeng; Chen, Yongzhen; Ni, Zhekan; Ye, Fan; Ren, Junyan

doi:10.1109/apccas.2018.8605568

Cited by 10 publications

(1 citation statement)

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“…In addition to time-interleaving, there have been several successful attempts to improve the speed of the single SAR ADC to obtain a further increase in bandwidth. Common ideas for increasing the sample rate are enhancing the SAR speed [3], using a faster sub-ADC to solve some bits [4] or using asynchronous logic to minimize conversion time [5].…”

Section: Introductionmentioning

confidence: 99%

A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps

Tenhunen

Spoof

Unnikrishnan

et al. 2022

2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)

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This paper presents a wideband 8-way timeinterleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.

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Section: Introductionmentioning

confidence: 99%