Spatial diversity advantages such as improved signal-to-noise ratio and in-band blocker filtering can be achieved through beamforming in the digital and/or analog domain. Digital beamforming benefits from the precision and efficient parallelization of digital signal processing. On the other hand, analog beamforming allows the filtering of in-band but out-of-beam blockers before the ADC which can improve the dynamic range performance of the receiver. A delay method based on resampling has recently emerged as a viable solution for enabling true-time-delay analog beamforming receivers, which overcome the fractional bandwidth limitation of phase-shift beamforming due to beam squint. This paper presents a 22-nm CMOS receiver prototype that enables reconfiguration between true-time-delay analog and digital beamforming to allow choosing the more suitable operation mode in different signal environments. The reconfigurability is achieved by exploiting the time-interleaved nature of both the resampling delay setup and high speed ADCs. In addition to the beamforming mode reconfigurability, the receiver achieves stateof-the-art 2 GHz instantaneous beamformed bandwidth in the analog mode. The receiver reaches a 100% fractional bandwidth at the low end of the 1-6 GHz frequency range.INDEX TERMS Analog beamforming, beam squint, CMOS, digital beamforming, integrated circuit, phased array, radio receiver, spatial filtering, true-time-delay.
This paper presents a wideband 8-way timeinterleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.
Modern wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this paper, we introduce a blocker tolerant harmonic rejection receiver which is able to suppress blockers at the local oscillator harmonics. The suppression is achieved by applying harmonic rejection in two stages, such that the first harmonic rejection already occurs at the first gain stage output. The proposed receiver achieves this harmonic rejection with simple 6-phase local-oscillator (LO) clocking. The proposed design also uses simple gain coefficients of ±1 while implementing harmonic rejection in two stages compensates for the mismatch effects of each stage. In addition, near-band blocker linearity is improved by implementing a 3rdorder baseband feedback response which acts in conjunction with N-path filtering. Implemented in a 28 nm FDSOI process, the receiver demonstrates 18-37 dB harmonic rejection from the first stage and 46-53 dB of harmonic rejection in total. Further, a blocker compression point of 2.5 dBm for a third harmonic blocker and a near-band blocker compression point of-6.5 dBm is achieved.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.