AMULET1: an asynchronous ARM microprocessor

Woods, J.V.; Day, P.; Furber, Steve; Garside, Jim; Paver, N.C.; Temple, Steve

doi:10.1109/12.588033

Cited by 66 publications

(30 citation statements)

References 7 publications

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“…The execution unit consists of two major stages, namely Decode2 (Dec2-Ctr12), which controls the operation of the shifter and multiplier units of the processor, and Decode3 (Dec3-Ctr13), which controls the ALU. Detailed descriptions of the AMULET1 microprocessor are provided in [46,60]. and Decode3 model the two major components of the execution unit of the processor.…”

Section: Modelling Amulet1: the Occarm Modelmentioning

confidence: 99%

Distributed Simulation of Asynchronous Hardware: The Program Driven Synchronization Protocol

Theodoropoulos

2002

Journal of Parallel and Distributed Computing

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Section: Modelling Amulet1: the Occarm Modelmentioning

confidence: 99%

Distributed Simulation of Asynchronous Hardware: The Program Driven Synchronization Protocol

Theodoropoulos

2002

Journal of Parallel and Distributed Computing

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“…To this end, we propose to adjust the clock period on a cycleby-cycle basis, ideally according to (2). The corresponding architecture, as shown in Fig.1 clock generator (CG) accordingly in each cycle.…”

Section: A Instruction Based Clock Adjustmentmentioning

confidence: 99%

“…However, even though the success of pioneering early work [2] in that field showed noticeable speedup and even power savings, the lack of a consistent methodology and reliable tools, as well as considerable design risks led industry to effectively abandon the asynchronous design approach.…”

Section: A Related Workmentioning

confidence: 99%

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Constantin

Wang

Karakonstantis

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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. (2015). Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment. In ProceedingsDesign, Automation and Test in Europe, 2015 (pp. 381-386 Publisher rights © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. General rightsCopyright for the publications made accessible via the Queen's University Belfast Research Portal is retained by the author(s) and / or other copyright owners and it is a condition of accessing these publications that users recognise and abide by the legal requirements associated with these rights. Abstract-Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28 nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

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Section: Modelling Amulet1: the Occarm Modelmentioning

confidence: 99%

Simulating asynchronous hardware on multiprocessor platforms: the case of AMULET1

Theodoropoulos

2001

Concurrency and Computation

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SUMMARYSynchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Hence, recently, there has been a resurgence of interest in asynchronous digital design techniques which promise to liberate digital design from the inherent problems of synchronous systems. This activity has revealed a need for modelling and simulation techniques suitable for the asynchronous design style. The concurrent process algebra communicating sequential processes (CSP) and its executable counterpart, occam, are increasingly advocated as particularly suitable for this purpose. This paper focuses on issues related to the execution of CSP/occam models of asynchronous hardware on multiprocessor machines, including I/O, monitoring and debugging, partition, mapping and load balancing. These issues are addressed in the context of occarm, an occam simulation model of the AMULET1 asynchronous microprocessor; however, the solutions devised are more general and may be applied to other systems too.

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AMULET1: an asynchronous ARM microprocessor

Cited by 66 publications

References 7 publications

Distributed Simulation of Asynchronous Hardware: The Program Driven Synchronization Protocol

Distributed Simulation of Asynchronous Hardware: The Program Driven Synchronization Protocol

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Simulating asynchronous hardware on multiprocessor platforms: the case of AMULET1

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