AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications

Ishihara, Tohru; Yamaguchi, S.; Ishitobi, Yuriko; Matsumura, Toshiro; Kunitake, Yuji; Oyama, Yuichiro; Kaneda, Y.; Muroyama, Masanori; Sato, Toshinori

doi:10.1109/sasp.2008.4570790

Cited by 14 publications

(4 citation statements)

References 11 publications

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“…The execution costs of each node on different processor are shown in Table 3, which under the condition of each task run at available maximum frequency. According to the previous study [32], frequency switching takes a negligible amount to time, about 189µs -300µs. These overheads are not consided in this study while applying the DVFS technique.…”

Section: Application Modelmentioning

confidence: 94%

Joint optimization of energy efficiency and system reliability for precedence constrained tasks in heterogeneous systems

Zhang

et al. 2016

International Journal of Electrical Power & Energy Systems

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Voltage scaling is a fundamental technique in the energy efficient computing field. Recent studies tackling this topic show degraded system reliability as frequency scales. To address this conflict, the subject of reliability aware power management (RAPM) has been extensively explored and is still under investigation. Heterogeneous Computing Systems (HCS) provide high performance potential which attracts researchers to consider these systems. Unfortunately, the existing scheduling algorithms for precedence constrained tasks with shared deadline in HCS do not adequately consider reliability conservation. In this study, we design joint optimization schemes of energy efficiecy and system reliability for directed acyclic graph (DAG) by adopting the shared recovery technique, which can achieve high system reliability and noticeable energy preservation. To the best of our knowledge, this is the first time to address the problem in HCS. The extensive comparative evaluation studies for both randomly generated and some real-world applications graphs show that our scheduling algorithms are compelling in terms of enhancement of both system reliability and energy saving.

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Section: Application Modelmentioning

confidence: 94%

Joint optimization of energy efficiency and system reliability for precedence constrained tasks in heterogeneous systems

Zhang

et al. 2016

International Journal of Electrical Power & Energy Systems

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“…For power evaluation, we assume the frequency-voltage specification (200MHz-1.0V and 100MHz-0.72V) of AMPLE processor [7]. The variation-affected ALUs and short-latency iALUs work at 1.0V and the long-latency unaffected iALUs work at 0.72V.…”

Section: Evaluation Methodologymentioning

confidence: 99%

Uncriticality-directed scheduling for tackling variation and power challenges

Sato

Watanabe

2009

2009 10th International Symposium on Quality of Electronic Design

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The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability. Increasing the supply voltage to reduce the delay should not be a solution, since it increases power consumption, which is another serious problem in microprocessor designs. This paper proposes to combine recently-proposed configurable latency technique with an instruction scheduling technique considering instruction uncriticality. While relying only on the configurable latency technique degrades processor performance, the combination maintains it by executing only uncritical instructions in the long-latency units. The uncriticality-directed technique is extended for power reduction. This can be achieved by decreasing supply voltage for some variation-unaffected units. Detailed simulations show that the proposed scheduling technique improves processor performance by 7.0% on average over the conventional scheduling and that performance degradation from a variation-free processor is only 2.3% on average, when 2 of 4 integer ALUs are affected by variations. It also improves energy efficiency by 9.9% on average.

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“…The following three types of processors have been used in the experiments validating our approach in [1]: (1) M32R-II, a 32-bit RISC microprocessor originally developed by Renesas Technology Corporation, (2) SH3-DSP, a 32-bit RISC microprocessor of Renesas Technology Corporation, and (3) multiperformance processor [22,23] which is based on Media embedded Processor (MeP) developed by Toshiba. All of the above three microprocessors have on-chip cache memories and scratch-pad memories (SPMs).…”

Section: A Targetmentioning

confidence: 99%

Processor Energy Characterization for Compiler‐Assisted Software Energy Reduction

Gauthier

Ishihara

2012

Journal of Electrical and Computer Engineering

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Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. The paper presents our recent research activities and results on characterizing and reducing the energy consumption in embedded systems. Firstly, a technique for characterizing the energy consumption of embedded processors during an application execution is presented. The technique trains a per-processor linear approximation model for fitting it to the energy consumption of the processor obtained by postlayout simulation. Secondly, based on the energy model mentioned above, the paper shows techniques for reducing the energy consumption by optimally mapping program code, stack frames, and data items to the scratch-pad memory (SPM) of the processor memory space.

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AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications

Cited by 14 publications

References 11 publications

Joint optimization of energy efficiency and system reliability for precedence constrained tasks in heterogeneous systems

Joint optimization of energy efficiency and system reliability for precedence constrained tasks in heterogeneous systems

Uncriticality-directed scheduling for tackling variation and power challenges

Processor Energy Characterization for Compiler‐Assisted Software Energy Reduction

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