Alternative techniques to reduce interface traps in n‐type 4H‐SiC MOS capacitors

Abstract

Several alternative oxidation techniques are developed and tested with the aim to reduce the high density of interface traps Dit in n‐type 4H‐SiC MOS capacitors. A lamp furnace in combination with a microwave plasma is employed to grow thin oxide layers, which are used for an insulating stack (SiO2 and Al2O3). The treatment of the oxide with nitrogen is another way to lower Dit. We introduce N atoms prior to the oxidation by ion implantation. During the oxidation process, the implanted N‐profile is redistributed; a considerable amount of the implanted N is accumulated at the SiC/SiO2‐interface, which leads to a strong reduction of Dit and a large negative flatband voltage. The negative flatband voltage can largely be compensated by coimplantation of aluminum. A model is proposed, which explains the passivation of interface traps in n‐type 4H‐SiC MOS capacitors. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Structural and electronic properties of the transition layer at the SiO2/4H-SiC interface

“…Our findings are in good agreement with previous experimental research in which only three different types of traps (dangling bonds, carbon clusters, and intrinsic traps in SiO 2 ) were considered to cause defect states at SiO 2 /SiC interfaces. 18 We may therefore conclude that the contributions of the interfacial transition layer to defect states depend mainly on dangling bonds and carbon clusters.…”

“…[5][6][7][8][9][10][11] Considerable effort has been devoted to the identification and characterization of interface defects at the SiO 2 /SiC interface. 6,[12][13][14][15][16][17][18][19][20][21] These investigations drew a conclusion that intrinsic oxide defects and excess carbon are the most dominant contributions to interface states. Intrinsic defects in SiO 2 that are independent of the polytype and orientation of SiC substrate, can account for the D it near the bottom of the SiC conduction band gap, so-called near-interface trap (NIT) levels.…”

Tailoring Oxide/Silicon Carbide Interfaces: NO Annealing and Beyond

“…The amount of N atoms can be tuned by implantation dose and energy. Studies have revealed that similarly to NO POA, the higher the nitrogen density at the thermally-formed interface, the lower the D it , and the higher the field-effect mobility [42,91,93]. In fact, Poggi et al have reported about an order of magnitude reduction of electrically active defects close to the conduction band edge of 4H-SiC and a room temperature field-effect mobility of up to 42 cm 2 /V.s in lateral nFETs fabricated on the (0001) surface [94,95], Fig.…”

Gate Stack Reliability of High-Mobility 4H SiC Lateral MOSFETs with Deposited Al2O3 Gate Dielectric

“…It is reported that Al 2 O 3 on SiC can have D it levels similar to that of thermally oxidized SiC [8]. Additionally, some reports in literature claim extremely high mobility values (300 cm 2 /V·s) and positive V T with deposited dielectrics [9], pushing the search towards alternative gate stack fabrication approaches.…”