Gate Stack Reliability of High-Mobility 4H SiC Lateral MOSFETs with Deposited Al₂O₃ Gate Dielectric

Abstract

Lateral nMOSFETs have been fabricated on 4H-SiC utilizing deposited dielectrics and gate-last processing. A bi-layer dielectric was utilized consisting of thin nitrided SiO 2 covered by 25nm of Al 2 O 3 deposited using atomic layer deposition. Fieldeffect mobility and threshold voltage (V T ) were found to vary with SiC nitric oxide (NO) anneal temperature. High peak mobility values of 106 cm 2 /V·s were obtained, with a corresponding V T of 0.8 V, using an 1175 °C 20 min NO anneal of the SiC before Al 2 O 3 deposition. Constant voltage stressing (CVS) of the gate (3 MV/cm) for 1000s induces a V T increase of only 0.12 V for the devices stressed at RT, whereas a V T shift of 0.34 V occurs for devices stressed at 150 °C. Heating unstressed devices to 200 °C reveals a stable V T with temperature. Negative charge in the gate region allows for the attainment of positive V T , while V T stability does not suffer.

Tailoring Oxide/Silicon Carbide Interfaces: NO Annealing and Beyond

“…Most importantly, it does not possess the same dominating trap level as SiO 2 , so that high electron mobility can be achieved in n-channel devices. Indeed, peak field-effect mobility values measured at room temperature on the Si-face can exceed 100 cm 2 /V.s [60,79]. A key observation is again that a thin thermal SiO or SiON layer is still required, not so much to reduce gate leakage but to increase efficiency by providing a progressive transition between the semiconductor and the deposited oxide.…”