Almost optimum placement legalization by minimum cost flow and dynamic programming

Abstract

VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (detailed placement or legalization).We consider algorithms for legalization. In particular, we analyze a generic legalization algorithm based on minimum cost flows and dynamic programming. Specializations are being used in industry for many years, and an improved version was proposed very recently in [2]. The objective of all these algorithms is to minimize the weighted sum of (squared) movements, i.e. they assume the placement to be already optimized except for not being legal.To evaluate results, we propose two different lower bounds for the legalization problem, one based on linear assignment, and the other one based on an integer linear programming relaxation. We prove that the second lower bound is always at least as good as the first one. We also show how to compute the bounds efficiently. We then give an extensive experimental analysis of the algorithms and the lower bounds by testing them on a set of recent industrial ASICs with up to 2.4 million cells. In particular, we show that the gap between the new algorithm and the better lower bound is usually less than 10 percent. This proves that the legalization problem is solved almost optimally.Besides (weighted) total (squared) movement, we also consider various other objectives like wirelength, timing, and routability. Our experiments demonstrate that minimizing total (weighted, squared) movement has almost no negative effect on the timing properties, routability and netlength. Therefore the new algorithm will help in overall design closure.

BonnTools: Mathematical Innovation for Layout and Timing Closure of Systems on a Chip

“…Experimental results show that the gap between a computed solution and a theoretical lower bound is only approximately 10%, and neither timing nor routability is significantly affected [6].…”

Large-scale circuit placement

“…Instead, it directly alters the quadraticwirelength objective to minimize the sum of all cells' displacements from their assigned subregions. The following four steps are then repeated until subregions become small enough that legalization and detailed placement by local perturbations can be applied [Brenner et al 2004].…”

“…This observation has renewed interest in improved methods for legalization [Li and Koh 2003;Agnihotri et al 2003;Khatkhate et al 2004] and detailed placement [Brenner et al 2004;Ramachandaran et al 2005]. Nevertheless, progress in global placement still continues to be made.…”

SafeResynth: A new technique for physical synthesis

“…A number of recent publications address precisely the issue of stability in physical synthesis optimizations. For example, Li et al [21] propose an incremental placement algorithm which maintains the stability of placement for gate sizing and buffer insertion, while Luo et al [24] and Brenner et al [4] address this same problem by designing legalizer tools that seek to preserve performance metrics. However, these approaches tend to break down in later stages of physical design, when circuits are heavily optimized.…”