SafeResynth: A new technique for physical synthesis

Abstract

Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design, often because they neglect important physical aspects of the layout, such as long wires or routing congestion. Our work defines and explores the concept of physical safeness and evaluates empirically its impact on route length, via count and timing. In addition, we propose a new physically safe and logically sound optimization, called SafeResynth, which provides immediately-measurable improvements without altering the design's functionality. SafeResynth can enhance circuit timing without detrimental effects on route length and congestion. We achieve these improvements by performing a series of netlist transformations and re-placements that are individually evaluated for logical soundness (that is, they do not alter the logic functionality) and for physical safeness. When used alone, SafeResynth improves circuit delay of IWLS'05 benchmarks by 11% on average after routing, while increasing route length by less than 0.2%. Since transistors are not affected by SafeResynth, it can also be applied to post-silicon debugging, where only metal fixes are possible. 1

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths

“…The drawback of the scheme is that the physical synthesis and logic optimization of the scheme are not tightly combined but are serial and performed one after another. In [7], the authors emphasize on the effectiveness of safe netlist transformations which do not create any illegal cell overlap during resynthesis.…”

Formal reset recovery slack calculation at the register transfer level

“…In particular, reset recovery delays due to long reset nets can cause registers to enter metastable states and corrupt reset correctness. One solution is to use physical design methods but doing so can perturb existing timing optimizations [5]. Another solution is to reset only part of the registers [7].…”

Wrip

“…Besides the global placement framework, incremental placement and post-placement optimization algorithms are also proposed in [7,8]. An incremental placer starts with an initial placement as its input, and focuses on further optimization for wirelength, timing, or other objectives.…”

“…A timing-driven incremental placement is proposed in [7] that uses linear programming to meet delay constraints. In [8], a safe netlist transformations which do not create any illegal cell overlap during the incremental placement is proposed.…”

“…In the prior arts, most global placement or incremental placement methods focus on placing cells at better locations to improve total wirelength or timing while little logic restructuring technique is involved to further optimize the placement. There exists little study on combining logical and physical synthesis [8,10]. Furthermore, these approaches suffer from the runtime issue caused by the high complexity of logic restructuring algorithms which prevents the industrial placer from fully combining with these logical restructuring techniques.…”