Allocating rotating registers by scheduling

Abstract

A rotating alias register file is a scalable hardware support to detect memory aliases at run-time. It has been shown that it can enable instruction-level parallelism to be effectively exploited from sequential code. Yet it is unknown how to apply it to loops. This paper presents an elegant and efficient solution that allocates rotating alias registers for a software-pipelined schedule of a loop. We show that surprisingly, this specific register allocation problem can be reduced to another software pipelining problem, for which numerous efficient algorithms are available. This is interesting in both theory and practice. We propose an algorithmic framework to solve the problem. We also present a simple software pipelining algorithm that specially targets register allocation. Comparison with a few other algorithms shows that it usually achieves the best allocation at the least time cost.Finally, we generalize the approach to allocate generalpurpose (integer/floating-point/predicate) rotating registers by showing that it is also a software pipelining problem.

Enabling Efficient Alias Speculation

“…With coalescing, Algorithm 1 constructs the checking graph with Aj acting as a proxy for A; all checking and anti-checking edges which would have been incident on A are instead incident on Aj. Incremental Construction of Checking Graph (Algorithm 1, lines [8][9][10][11][12][13][14][15][16][17][18][19][20][21]: Checking edges go backwards in the schedule while anti-checking edges go forward. Therefore, unscheduled instructions are inspected for checking edges while instructions already scheduled are inspected for anti-checking edges.…”

“…Prior proposals make use of an alias register mechanism for alias detection in hardware [3,6,9,11,18,21]. For instance, Itanium uses the Advanced Load Address Table (ALAT) [3] for memory alias detection.…”

“…Rong et al [18] propose an efficient register allocation scheme for such a rotating alias register file-based memory alias detection technique that formulates register allocation as a software pipelining problem. This work implements alias coalescing on top of the SMARQ alias register allocation algorithm.…”

“…Past alias speculation proposals [3,4,6,7,11,13,14,18,21] either (i) encode memory access ranges (base address and size of access) of instructions using a signature (e.g. a Bloom filter [15,20]), or (ii) encode the memory access range of each instruction individually in an "alias register".…”