Gaussian networks are gaining popularity as good candidates Network On-Chip (NoC) for interconnecting Multiprocessor System-on-Chips (MPSoCs). They showed better topological properties compared to the 2D torus networks with the same number of nodes N and the same degree 4. All-to-all broadcast is a collective communication algorithm used frequently in many parallel applications. Recently, Z. Zhang et al. [1] have proposed an all-to-all broadcast algorithm for Gaussian on-chip networks that achieves the minimum delay time but requires 4k extra buffers per router, where k is the network diameter. In this paper, we propose a new all-toall broadcast algorithm for dense Gaussian on-chip networks that achieves the minimum delay time without requiring any extra buffers per router. In this paper, we propose a new all-to-all broadcast algorithm for dense Gaussian on-chip networks that achieves the minimum delay time without requiring any extra buffers per router. Along with low latency, reducing the amount of buffer space and power consumption are very important issues in NoCs architectures.Index Terms-Network-on-Chip (NoC), Gaussian networks, all-to-all broadcasting, spanning trees Ç 1 INTRODUCTION T HE scale down of transistor technology allows microelectronics manufacturers to embed more sophisticated systems on a single micro-chip (SoC) [2], [3], [4], [5], [6], [7].On chip integration is becoming popular not only in the Chip Multi Processor (CMP) research area but also in the wider range of nowadays devices such as cell-phones, smart-phones, smart-houses and vehicle embedded systems, etc.As the number of cores increase in CMP, the system performance begins to be affected by on-chip interconnects. The widely used bus structures (shared bus, hierarchal bus, and bus matrix) are becoming a limiting factor for performance, space and energy consumption [5]. In order to overcome the disadvantages of bus structures, they are being replaced by Network-on-Chip (NoC). NoC architectures are an attempt to scale down the concepts of large-scale networks, and apply them in the embedded system-on-chipSoC) domain [8], [9], [10], [11], [12], [13]. A NoC is an onchip communication network used to route data from a source Processing Element (PE) to a destination PE via a network fabric that consists of switches (routers) and interconnection links (wires) [8]. NoC interconnects address scalability issues and provide a low latency communication layer, higher bandwidth, and communication parallelism. Among the most popular NoC topologies developed for CMPs such as n-dimensional mesh, torus, folded torus, hypercube, and octagon, low-dimensional networks, like 2D-mesh and 2D-torus, offer better performance in terms of higher throughput and lower latency than high-dimensional networks (high dimensional k-aryn-cubes and meshes) [13], [14]. Recently, two other wrap-around networks have been proposed as suitable alternatives to the 2D torus network: the degree 4 Gaussian networks [15], [16], [17] and the degree 6 Eisenstein-Jacobi (EJ) networks [...