All-optical lithography process for contacting nanometer precision donor devices

Abstract

We describe an all-optical lithography process that can be used to make electrical contact to atomic-precision donor devices made in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.Keywords: Methods of micro-and nanofabrication and processingThe ability to fabricate devices with atomic precision holds promise for revealing the key physics underlying everything from quantum bits 1,2 to ultra-scaled digital circuits 3-7 . A common atomic-precision fabrication (APFab) pathway uses a scanning tunneling microscope (STM) to create lithographic patterns on a hydrogenpassivated Si(100) surface 8 . Phosphine gas introduced into the vacuum system selectively adsorbs on sites where Si dangling bonds have been re-exposed by patterning 9 , yielding atomically precise, planar structures made of P donors. Unlike electron beam lithography (EBL), which can pattern hydrogen with a resolution of around 100 nm and is unable to image the pattern 10 , the STM is an ideal instrument for this process because it can both pattern and image the hydrogen resist with atomic precision 11 . However, STMs are typically capable of patterning devices only up to 10 µm by 10 µm in size, which are too small to directly contact. A post-patterning microfabrication process, consisting of etching via holes in an encapsulating Si overlayer and then depositing metal in direct contact with the planar donor layer, is used to make electrical contact to the devices. Even the largest features made with the STM are small enough that this contacting process relies on EBL for patterning and 200 nm-scale processing. At this scale, making good electrical contact between a deposited metal and an atomically-thin onedimensional line of donors at the edge of an etched hole is challenging, and even successful EBL process flows in this application are rate-limiting.In this paper, we detail an all-optical lithography contacting process that reduces the time of fabricating an atomic-precision device by an order of magnitude. This is made possible by the integration of both ion-implanted contacts and metal alignment marks in the starting material, which bridge the scale between the largest regions accessible by STM and the smallest length scale accessible by low-cost photolithography. Specifically, the ionimplanted contacts neck down to a small enough area that the STM can place the APFab device in direct contact with them, and extend out to a region large enough

The impact of stochastic incorporation on atomic-precision Si:P arrays

“…PH 3 is introduced into the UHV chamber via a precision leak valve, with PH 3 coverage calculated using the partial pressure of the PH 3 introduced during dosing measured by an RGA (specifically the 34 amu fragment). In a typical process, a PH 3 partial pressure of 3.0×10 −10 Torr is introduced for 10 minutes at room temperature, resulting in a coverage of 0.15 Langmuir, which has been previously demonstrated to provide sufficient coverage for atomically precise donor structures [54,55]. While the partial pressure reported through the PH 3 RGA value may represent a lower bound on the actual partial pressure introduced, the reported dosing conditions have also been demonstrated to provide the expected 0.25 ML coverage on a clean Si(100) surface for P incorporated at 310 • C [56], further demonstrating that the dosing conditions utilized will result in sufficient coverage in the depassivated windows.…”

Low-Resistance, High-Yield Electrical Contacts to Atom Scale Si:P Devices Using Palladium Silicide

“…Preimplanted contact resistances have been reported ranging as high as 48 kΩ [9] with the lowest published contact resistivity being approximately 1kΩ μ m, a value approximated from a two-point resistance measurement. [10] The Pd 2 Si contacts reported here offer an order of magnitude improvement over typical contact resistances and a substantial improvement in contact variability.…”

“…In one case, vias are reported to provide contact resistances <100 kΩ. [8] Another approach is the formation of preimplanted contacts, which are then relocated in situ so that device contacts are written to overlap with the preimplanted surface [9,10]. While this approach has met with success, it restricts the thermal budget for UHV processing and gives a high parasitic resistance compared to metal contacts of the same dimensions.…”

CMOS platform for atomic-scale device fabrication

“…As a result, only a handful of groups in the world have successfully made devices with this technique [3,9,14,15], and despite efforts directed at simplifying some parts of the process [16,17] its current application potential remains somewhat limited.…”