2019
DOI: 10.1103/physrevapplied.11.034071
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Low-Resistance, High-Yield Electrical Contacts to Atom Scale Si:P Devices Using Palladium Silicide

Abstract: Scanning tunneling microscopy (STM) enables the fabrication of two-dimensional δ-doped structures in Si with atomistic precision, with applications from tunnel field-effect transistors to qubits. The combination of a very small contact area and the restrictive thermal budget necessary to maintain the integrity of the δ layer make developing a robust electrical contact method a significant challenge to realizing the potential of atomically precise devices. We demonstrate a method for electrical contact using Pd… Show more

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Cited by 11 publications
(8 citation statements)
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“…The device is then epitaxially encapsulated with intrinsic Si by using an optimized locking-layer process to suppress dopant movement at the atomic scale during epitaxial overgrowth 12,14 . The sample is then removed from the UHV system and Ohmic-contacted with e-beam-defined palladium silicide contacts 15 .…”
Section: Discussionmentioning
confidence: 99%
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“…The device is then epitaxially encapsulated with intrinsic Si by using an optimized locking-layer process to suppress dopant movement at the atomic scale during epitaxial overgrowth 12,14 . The sample is then removed from the UHV system and Ohmic-contacted with e-beam-defined palladium silicide contacts 15 .…”
Section: Discussionmentioning
confidence: 99%
“…In this study, we overcome previous challenges by uniquely combining hydrogen lithography that generates atomically abrupt device patterns 10,11 with recent progress in low-temperature epitaxial overgrowth using a locking-layer technique [12][13][14] and silicide electrical contact formation 15 to substantially reduce unintentional dopant movement. These advances have allowed us to demonstrate the exponential scaling of the tunneling resistance on the tunnel gap separation in a systematic and reproducible manner.…”
mentioning
confidence: 99%
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“…We use a room-temperature grown locking layer technique to suppress atomic-scale movement of the precisely defined dopant atom positions 26 before a subsequent low-temperature (~250 °C) epitaxial Si overgrowth, that embeds the dopant atoms in a 3-dimensional crystalline Si environment. Finally, ohmic contacts to the buried electrodes are formed using a low thermal budget silicide contacting technique 27 .
Fig.
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Section: Resultsmentioning
confidence: 99%
“…These values are slightly lower than sheet resistance values reported for B δ-doped nanowires fabricated from B 2 H 6 9 and slightly higher compared to P δ-doped nanowires fabricated from PH 3 . 32,52 The higher sheet resistance of W2 is possibly due to the higher temperature anneal of the locking layer (400 °C) compared to that of W1 (350 °C). This would follow the trend observed with samples B2 and B3 with the higher temperature dose of B3 compared to B2 leading to a higher sheet resistance.…”
Section: ■ Experimental Methodsmentioning
confidence: 99%