All-Digital Quadrature Detection With TAD for Radio-Controlled Clocks/Watches

Masuda, Sumio; Watanabe, Toshio; Yamauchi, Shigenori; Terasawa, Tomohito

doi:10.1109/tcsi.2008.925950

Cited by 11 publications

(5 citation statements)

References 2 publications

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“…The digital output of TAD actually reflects the moving average of input voltage (V in,average ) during T s . This intrinsic 1st-order LPF feature has been theoretically analyzed and verified in [10].…”

Section: Time-to-digital Conversionmentioning

confidence: 82%

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology

Watanabe

Miyahara

et al. 2015

IEICE Trans. Fundamentals

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An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. All-digital structure is intrinsically compatible with the scaling of CMOS technology, and can satisfy the great demand of miniaturized and low-voltage sensor interface. The proposed TAD uses an inverter-based Ring-Delay-Line (RDL) to transform the input signal from voltage domain to time domain. The voltage-modulated time information is then digitized by a composite architecture namely "4-Clock-Edge-Shift Construction" (4CKES). TAD features superior voltage sensitivity and 1storder noise shaping, which can significantly simplify the power-hungry pre-conditioning circuits. Reconfigurable resolution can be easily achieved by applying different sampling rates. A TAD prototype is fabricated in 65 nm CMOS, and consumes a small area of 0.016 mm 2. It achieves a voltage resolution of 82.7 μV/LSB at 10 MS/s and 1.96 μV/LSB at 200 kS/s in a narrow input range of 0.1 Vpp, merely under 0.6 V supply. The highest SNR of TAD prototype is 61.36 dB in 20 kHz bandwidth at 10 MS/s. This paper also analyzes the nonideal effects of TAD and discusses the potential solutions. As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration.

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Section: Time-to-digital Conversionmentioning

confidence: 82%

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology

Watanabe

Miyahara

et al. 2015

IEICE Trans. Fundamentals

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“…Accordingly, the ADC (TAD) sampling clock frequency fs should be 160 kHz (4 x 40 kHz), which is generated from the external 32.768 kHz crystal oscillator clock using the ADPLL [7]. After ADC (TAD), the information for both Ic and Qc can be obtained digitally by applying the calculations mentioned in Section II in the DSP section [6]. The DSP section also performs digital low-pass filters and has a time code generator in the back-end logic section.…”

Section: Ic Configuration and Experimental Resultsmentioning

confidence: 99%

“…In order to achieve our new receiver prototype IC, we use two original methods: 1) the TAD-DQD (TAD DigitalQuadrature-Detection) [6], and 2) the ADPLL (All-Digital PLL) using a frequency multiplying number with decimals [7]. As for digital quadrature detection, the Time Analog-toDigital converter (TAD) [8]- [10] has features not found in conventional analog-to-digital converters (ADCs), including an all-digital and small-scale configuration, and continuous integration of input voltage Vin without any dead time.…”

Section: Introductionmentioning

confidence: 99%

“…Also a newly developed 0.18-m CMOS TAD is described. By performing simple digital calculations on the A/D converted value, TAD-DQD detects the amplitude and phase from a specific frequency carrier wave [6]. This method requires ADC (TAD) sampling clocks which are fourfold frequency clocks against carrier frequencies (fcar) such as 40 kHz, 60 kHz, 77.5 kHz and 68.5 kHz, respectively.…”

Section: Introductionmentioning

confidence: 99%

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An RCC receiver IC with TAD-DQD and ADPLL using frequency multiplying number with decimals

Watanabe

Masuda

Wakairo

2009

2009 IEEE International Frequency Control Symposium Joint With the 22nd European Frequency and Time Forum

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A 0.18-m CMOS RCC (radio-controlled clock) receiver IC with TAD (Time A/D converter) and ADPLL was realized. This IC, which receives low-frequency (LF) standard time waves, performs AM detection with digital circuits. It has two key components. First, TAD is an all-digital analog-todigital converter, whose voltage resolution is settable (15 V/LSB at 100kS/s and 3.1mV/LSB at 20MS/s). Second, the ADPLL applying a frequency multiplying number of 4.8828125 generates a 160 kHz ADC (TAD) sampling clock from a 32.768 kHz quartz-clock for digital detection processing. The DSP section, which operates as an adder-subtractor and digital filters, consists of standard cells (75,000 gates). This test IC achieved minimum detectable sensitivity of 0.7 Vrms and maximum detectable sensitivity of 100 mVrms for a standard time wave of 40 kHz at the LNA input terminal. Since the TAD sampling frequencies are settable with desirable multiplying numbers with decimals, the IC can receive different kinds of LF standard time waves such as 40 kHz (JP), 60 kHz (JP), 77.5 kHz (DE), and 68.5 kHz (CN) without any use of quartz-crystal filters.

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“…2 shows the block diagram of the RCC receiver. It consists of a low noise amplifier (LNA), I/Q demodulator with phase scanning (I/Q DPS) [1]- [2], all-digital clock generator (ADCG), inter integrated circuit (I 2 C), and a decoding circuit. This RCC receiver contains two main circuits.…”

Section: Introductionmentioning

confidence: 99%

A radio-controlled receiver for clocks/watches and alarm applications

Liu

Chiu

Peng

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a radio-controlled clock/alarm (RCC) receiver. The proposed RCC receiver adopts a signal transmitted technique via amplitude modulation (AM) principle. This I/Q DPS adopts a multi-phase sampled technique using a multi-phase ring oscillator. The decoding circuit can amplify the input signal and filter the noise signal to achieve high quality signal source. The low noise amplifier (LNA) circuit can receive the smaller input power. The operational frequency of all-digital clock generator (ADCG) is programmable for the broadcast frequency of local communication systems, such as the DCF77 (Germany), WWVB (US), JJY (Japan), BPC (CN), and MSF (UK). The digital loop filter of ADCG adopts a successiveapproximation register (SAR) algorithm for fast locking time.This RCC receiver is implemented in a 0.18 um CMOS process and the core area of RCC receiver is 1152 × 1572 μm 2 . The accuracies of operational frequencies of ADCG are less than ±264 ppm for all radio broadcasting frequencies. The voltage gain of LNA is 24.44 dB to achieve the lower input power. The measured environment of clock/alarm application is set and verified for the test chip of RCC receiver.

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All-Digital Quadrature Detection With TAD for Radio-Controlled Clocks/Watches

Cited by 11 publications

References 2 publications

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology

An RCC receiver IC with TAD-DQD and ADPLL using frequency multiplying number with decimals

A radio-controlled receiver for clocks/watches and alarm applications

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