All-digital delay-locked loop for 3D-IC die-to-die clock synchronization

Abstract

In this paper, an all-digital delay-locked loop (ADDLL) for 3D-IC die-to-die clock synchronization with through silicon vias (TSVs) is presented. The proposed ADDLL can tolerate delay variations in TSVs and synchronize the clock signals in multiple layers of a given 3D-IC. Firstly, after system is reset, the proposed ADDLL uses two high resolution delay lines which composed of digital controlled varactors (DCVs) to compensate for the delay variations in TSVs. Subsequently, the proposed ADDLL can further compensate for the clock skew of clock signals in multiple layers of a 3D-IC. After ADDLL is locked, the clock skew or phase error is eliminated, and data transfer between dies can be performed synchronously. The proposed design can operate from 300MHz to 1GHz. The proposed ADDLL is implemented in a standard performance 90nm CMOS process, and the area of the ADDLL per die is 0.045mm 2 . The power consumption of the proposed ADDLL is 3.27mW at 1GHz, and the maximum phase error of clock signals in multiple layers of a given 3D-IC is 21.9ps.Index Term all-digital delay-locked loop, through silicon via (TSV), 3D-IC, digitally controlled delay line.

Repairing a 3-D Die-Stack Using Available Programmable Logic

“…Clock synchronization and clock deskewing across multiple dies in a 3D stacked IC is an active area of research [26]- [29]. A common approach to address the clock synchronization problem across multiple dies in a 3D stack is to use Delay-Locked Loops (DLLs) to drive the TSVs to help ensure that the local clock networks on each die are synchronized.…”

“…The clock synchronization circuitry has a very small area footprint (0.0044mm 2 ) and consumes only 1.8mW of power. Recently, an all-digital delay-locked loop (ADDLL) for 3D-IC die-to-die clock synchronization with TSVs was presented in [29]. The authors proposed ADDLLs with two high resolution delay lines with digital controlled varactors (DCVs) to compensate for the delay variations of two TSVs.…”