2017 IEEE International Symposium on Circuits and Systems (ISCAS) 2017
DOI: 10.1109/iscas.2017.8050431
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Design of a digital IP for 3D-IC die-to-die clock synchronization

Mehdi Sadi
1
,
Sukeshwar Kannan
2
,
Luke England
3
et al.
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Cited by 8 publications
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