Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture

Sánchez-Élez, M.; Du, Huibin; Tabrizi, Nozar; Long, Yun; Bagherzadeh, Nader; Fernández, M.

doi:10.1016/s0097-8493(03)00143-2

Cited by 10 publications

(9 citation statements)

References 21 publications

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“…We have used the MG architecture to test these experiments and developed an interactive ray tracing algorithm for it [9]. Ray tracing involves projecting rays into the computational model of 3D space and resolving intersections and occlusions to define what color to display at each point of the screen.…”

Section: Resultsmentioning

confidence: 99%

“…The number of coherent PEs is usually small. In this paper we suppose that our application has 1×N coherence which, for example, is the case of ray tracing in MorphoSys [9], all the PEs in the same row (column) are supposed to be coherent. Moreover, a study in 1×N can be easily extrapolated to the K×N and the N×N cases.…”

Section: Data Coherencementioning

confidence: 99%

“…Another study of loop execution appears in [8], but focuses on the usage of memory operations sharing. A brief study of tree execution onto these architectures appears in [9]. However, this paper does not find an optimum mapping scheme because it focuses in ray tracing algorithm optimization.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures

Rivera

Sánchez-Élez

Fernández

et al. 2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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Reconfigurable architectures have become increasingly important in recent years. In this paper we present an approach to the problem of executing 3D graphics interactive applications onto these architectures. The hierarchical trees are usually implemented to reduce the data processed, thereby diminishing the execution time. We have developed a mapping scheme that parallelizes the tree execution onto a SIMD reconfigurable architecture. This mapping scheme considerably reduces the time penalty caused by the possibility of executing different tree nodes in SIMD fashion. We have developed a technique that achieves an efficient hierarchical tree execution taking decisions at execution time. It also promotes the possibility of data coherence in order to reduce the execution time. The experimental results show high performance and efficient resource utilization on tested applications.

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Section: Resultsmentioning

confidence: 99%

Section: Data Coherencementioning

confidence: 99%

See 1 more Smart Citation

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures

Rivera

Sánchez-Élez

Fernández

et al. 2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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“…Previous research has proposed several hardware models for realtime raytracing [15], [16], [17] offering very good performance for the sample scenes used by executing certain software constructs directly in hardware.…”

Section: Existing Hardware Modelsmentioning

confidence: 99%

CREMA: Fusing Memory and Processing for Parallel Raytracing

Ochsenfahrt

Salomon

2007

EUROCON 2007 - The International Conference on "Computer as a Tool"

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Under certain conditions, accelerator data structures significantly reduce a raytracer's runtime. But for most of them, unfortunately, the literature does not provide any a priori indication of whether or not they yield any speedup at all in a particular scene. For others though, the literature does provide lower bounds, but those accelerators are of rather theoretical utility. A straight forward analysis indicates that both the sequential processing and memory accesses constitute an inherent bottleneck for any of the software-centered raytracers. By contrast, this paper proposes a parallel hardware architecture, which renders a scene in constant time O(1) per ray, regardless of the scene's size and complexity. A prototypical implementation on a field-programmable gate array validates the architecture's feasibility and provides first laboratory results.

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“…A study of 3D graphics execution on coarse-grain reconfigurable architectures appears in [7]. In this paper the authors focus on ray tracing algorithm optimizations but they do not deal with a power effective execution model.…”

Section: Introductionmentioning

confidence: 99%

Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures

Rivera

Sánchez-Élez

Fernández

et al.

19th IEEE International Parallel and Distributed Processing Symposium

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In this paper we present a data prefetch policy for the execution of 3D interactive applications on coarse-grain reconfigurable architectures. User's actions not occurring at expected times combined with the volume of data involved in this kind of applications impact strongly in performance. We define a data prefetch scheme to avoid reconfigurable processing unit stalls due to operands unavailability through profiling methodologies and special search algorithms. Experimental results satisfy time constraints of interactive applications and show a power effective solution for them.

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Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture

Cited by 10 publications

References 21 publications

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures

CREMA: Fusing Memory and Processing for Parallel Raytracing

Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures

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