Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures

Abstract

Reconfigurable architectures have become increasingly important in recent years. In this paper we present an approach to the problem of executing 3D graphics interactive applications onto these architectures. The hierarchical trees are usually implemented to reduce the data processed, thereby diminishing the execution time. We have developed a mapping scheme that parallelizes the tree execution onto a SIMD reconfigurable architecture. This mapping scheme considerably reduces the time penalty caused by the possibility of executing different tree nodes in SIMD fashion. We have developed a technique that achieves an efficient hierarchical tree execution taking decisions at execution time. It also promotes the possibility of data coherence in order to reduce the execution time. The experimental results show high performance and efficient resource utilization on tested applications.

Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures

“…For a typical N×N reconfigurable array there are several possible parallel schemes [8]. Our prefetch proposal supposes that our application has 1×N coherence.…”

“…There are several possible mapping solutions as were exposed in [8]. The most adequate in terms of data coherence expllitation, time and power is the following one:…”

“…In this paper the authors focus on ray tracing algorithm optimizations but they do not deal with a power effective execution model. An in-depth analysis of coherent mapping solutions for 3D graphics applications onto reconfigurable architectures was done in [8].…”