Algorithm based on modified threaded binary tree for estimating delay affected by internal charges in CMOS gates

Chang, Meng‐Chou; Yih, Shuih-Jong; Feng, Wu‐Shiung

doi:10.1049/el:19961237

Cited by 3 publications

(3 citation statements)

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“…The delay due to the internal charges can be calculated approximately as dt= Q/L= (Q/V7)2R ( 5 ) where I,, is the average current, V, is the voltage swing, R is the effective resistance of the conducting path and Q is the charge stored in the internal nodes. More than one internal nodes may be going to charge or discharge in the series-parallel tree, and these nodes must be taken into account when calculating the switching delay.…”

Section: Vi-327 42 Internal Nodesmentioning

confidence: 99%

“…Thus, Eq. 5 is rewritten as Di=E 2R,(QJV,) (6) where Ri is the effective resistance of internal node v, with respect to ground, Qi is the charge stored in the internal node After all, the total delay is summed up by the delay times caused by the effect of overshoot and the internal nodes, including the charge sharing effect [5,6].…”

Section: Vi-327 42 Internal Nodesmentioning

confidence: 99%

“…Lin and Mead [4] proposed an efficient method that can be implemented in a recursive way. Furthermore, another important feature of BTS is that the delay and slope calculations are considered with internal charges and charge sharing effects [5,6]. The Internal charges stored in the internal nodes of a MOS circuit will increase the 7, R&D Rd.…”

Section: Introductionmentioning

confidence: 99%

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Waveform approximation technique in the switch-level timing simulator BTS

Chang

Chen

Wang

et al.

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

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In this paper an accurate and efficient switch-level timing simulator is described. The high accuracy is attributed to a new waveform approximation technique, which includes delay estimation and slope estimation. Efficient delay and slope calculations are accomplished through a switch-level simulation instead of using a transistor-level simulation. A new approach for delay estimation is presented, and it models the delay behavior of an RC tree by two equations: a dominant delay equation and an offset delay equation. Both are derived by a special process to fit the surface built by experimental data measured from the actual delay behavior of a CMOS gate. The results show good agreement with SPICE.

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Section: Vi-327 42 Internal Nodesmentioning

confidence: 99%