Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drops, etc. A new current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components:(1) Differential gate capacitor currents, (2) charging currents for load capacitance, and (3) short-circuit currents. The first one occurs when input changes and the others exist only when the output changes. Hence this model can generate negative current waveform, like SPICE. These three components are characterized with triangular functions with four parameters which can be easily obtained after a timing simulation. This model can be used in any switch-level timing simulators to generate current waveforms. The simulated current waveform, instead of the average estimation, helps solve VLSI reliability problems due to the electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE and our model, we can find that agreement occurs, especially between the time points of current pulses.
A new charge-based current model for CMOS gates is presented in this paper. The current during a transition consists of three components : one occurs when the input changes and the others ezist only when the output changes. So, this model can generate current waveform with negative values, like SPICE. These three components are characterized b y triangular functions with four parameters which can be easily obtained after timing simulation. When comparing the resulta obtained by wing SPICE with those b y our model, we find agreement, especially on the time points at which mazimum current occurs.
In this paper an accurate and efficient switch-level timing simulator is described. The high accuracy is attributed to a new waveform approximation technique, which includes delay estimation and slope estimation. Efficient delay and slope calculations are accomplished through a switch-level simulation instead of using a transistor-level simulation. A new approach for delay estimation is presented, and it models the delay behavior of an RC tree by two equations: a dominant delay equation and an offset delay equation. Both are derived by a special process to fit the surface built by experimental data measured from the actual delay behavior of a CMOS gate. The results show good agreement with SPICE.
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