Algorithm-architecture mapping for custom DSP chips

Loeffler, Charles M.; Ligtenberg, A.; Moschytz, G.S.

doi:10.1109/iscas.1988.15321

Cited by 26 publications

(10 citation statements)

References 3 publications

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“…1 (b) shows the operations performed in the rectangular blocks in Fig. 1 (a), which are labeled as kCn blocks where k = 1 or √ 2, and n = 1, 3, or 6 [3]. The complex multiplication operations included in these kCn blocks are simplified using AI encoding, as explained in Section 2.…”

Section: Loeffler Dct Algorithmmentioning

confidence: 99%

“…For a given data sequence x i , i = 0, 1, · · · , N − 1, its one-dimensional (1-D) N-point DCT, y m , m = 0, 1, · · · , N − 1, is defined as follows [3]:…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, K 0 is selected as √ 2, as in [3]. The efficiency of a DCT implementation can be evaluated based on its ability to produce DCT coefficients with a satisfactory precision as quickly as possible, using as little hardware as possible.…”

Section: Introductionmentioning

confidence: 99%

“…Traditionally, methods with less hardware are focused on minimizing the number of multiplication operations. The DCT algorithm introduced by Loeffler et al [3], called Loeffler algorithm below, is recognized as the most computationally efficient algorithm, because it requires the theoretically least number of multiplication operations. However, the 11 multiplications required by the Loeffler algorithm when calculating a 1-D 8-point DCT are still a burden for many applications.…”

Section: Introductionmentioning

confidence: 99%

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Pipelined implementation of AI-based Loeffler DCT

Shen

2013

IEICE Electron. Express

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Abstract:We propose a pipelined implementation of the eight-point Loeffler discrete cosine transform (DCT) for portable applications. The pipelined structure produces one DCT coefficient per clock cycle, which meets the limited memory bandwidth of many portable devices. Twodimensional algebraic integer (AI) encoding and the shift-and-add approach were used to make the implementation multiplication-free. A hardware cost reduction of approximately 40% was achieved by trading off the precision of the adders against a negligible amount of error in the reconstructed images.

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Section: Loeffler Dct Algorithmmentioning

confidence: 99%

“…For a given data sequence x i , i = 0, 1, · · · , N − 1, its one-dimensional (1-D) N-point DCT, y m , m = 0, 1, · · · , N − 1, is defined as follows [3]:…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Pipelined implementation of AI-based Loeffler DCT

Shen

2013

IEICE Electron. Express

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“…Each transform coefficient needs to be multiplied by a scale factor to make the resulting transform orthogonal. The design of the proposed transforms is fully recursive, coinciding with LLM factorizations for 4-point and 8-point transforms 18 . In odd parts we use a modification of Plonka-Tashe Type-IV DCT factorization 19 in which all factors are moved to the scaling stage 20 .…”

Section: ) Transforms For Inter-prediction Residualsmentioning

confidence: 99%

A hybrid video codec based on extended block sizes, recursive integer transforms, improved interpolation, and flexible motion representation

et al. 2011

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This paper describes video coding technology proposal submitted by Qualcomm Inc. in response to a joint call for proposal (CfP) issued by ITU-T SG16 Q.6 (VCEG) and ISO/IEC JTC1/SC29/WG11 (MPEG) in January 2010. Proposed video codec follows a hybrid coding approach based on temporal prediction, followed by transform, quantization, and entropy coding of the residual. Some of its key features are extended block sizes (up to 64×64), recursive integer transforms, single pass switched interpolation filters with offsets (single pass SIFO), mode dependent directional transform (MDDT) for intra-coding, luma and chroma high precision filtering, geometry motion partitioning, adaptive motion vector resolution. It also incorporates internal bit-depth increase (IBDI), and modified quadtree based adaptive loop filtering (QALF). Simulation results are presented for a variety of bit rates, resolutions and coding configurations to demonstrate the high compression efficiency achieved by the proposed video codec at moderate level of encoding and decoding complexity. For random access hierarchical B configuration (HierB), the proposed video codec achieves an average BD-rate reduction of 30.88℅ compared to the H.264/AVC alpha anchor. For low delay hierarchical P (HierP) configuration, the proposed video codec achieves an average BD-rate reduction of 32.96℅ and 48.57℅, compared to the H.264/AVC beta and gamma anchors, respectively.

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High-level algorithm and architecture transformations for DSP synthesis

Parhi

1995

Journal of VLSI Signal Processing

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Abstract.This survey paper reviews numerous high-level transformation techniques which can be applied at the algorithm or the architecture level to improve the performance of digital signal and image processing architectures and circuits implemented using VLSI technology. Successful design of VLSI signal and image processors requires careful selection of algorithms, architectures, implementation styles, and synthesis techniques. High-level transformations can play an important role in reducing silicon area or power at the same speed or in increasing the speed for same area. These transformations can also increase the suitability of an algorithm for a particular architectural style. The transformation techniques reviewed in this paper include pipelining, parallel processing, retiming, unfolding, folding, look-ahead, relaxed look-ahead, associativity, distributivity, and reduction in strength.

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Algorithm-architecture mapping for custom DSP chips

Cited by 26 publications

References 3 publications

Pipelined implementation of AI-based Loeffler DCT

Pipelined implementation of AI-based Loeffler DCT

A hybrid video codec based on extended block sizes, recursive integer transforms, improved interpolation, and flexible motion representation

High-level algorithm and architecture transformations for DSP synthesis

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