Algebraic integer based 8&amp;#x00D7;8 2-D DCT architecture for digital video processing

Madanayake, H.L.P. Arjuna; Cintra, Renato J.; Onen, D.; Dimitrov, Vassil S.; Bruton, L.T.

doi:10.1109/iscas.2011.5937796

Cited by 18 publications

(22 citation statements)

References 5 publications

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“…The proposed architecture consists of five sub-circuits [61]: (i) an input decimator circuit; (ii) an 8-point AI- (3) is obtained via wired cross-connections. The proposed architecture is shown in Fig.…”

Section: -D Ai Dct Architecturementioning

confidence: 99%

“…This transformation step operates at the reduced clock rate of F clock . Indeed, the resulting AI encoded data components are split in four channels according to their z 4 basis representation [61]. Such outputs are time-multiplexed mixed-domain partially computed spectral components.…”

Section: An 8-point Ai-encoded Arai Dct Corementioning

confidence: 99%

“…, 7 is the column index and k is the modular time index containing the information of the row number. In hardware, this means that the AI representation is contained in at most four parallel integer channels [61]. Some quantities are known beforehand to require less than four AI encoded integers (cf.…”

Section: An 8-point Ai-encoded Arai Dct Corementioning

confidence: 99%

“…The 2-D AI-DCT consists of an input section having a decimation structure, 1-D 8-point AI-DCT block for column-wise DCTs, a real-time AI-TB, four parallel 1-D 8-point AI-DCT blocks for row-wise DCTs, and an FRS[61]. encoded 1-D DCT block shown inFig.…”

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confidence: 99%

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A Row-Parallel 8$\,\times\,$8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

Madanayake

Cintra²,

Onen³

et al. 2012

IEEE Trans. Circuits Syst. Video Technol.

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An algebraic integer (AI) based time-multiplexed row-parallel architecture and two final-reconstruction step (FRS) algorithms are proposed for the implementation of bivariate AI-encoded 2-D discrete cosine transform (DCT). The architecture directly realizes an error-free 2-D DCT without using FRSs between row-column transforms, leading to an 8×8 2-D DCT which is entirely free of quantization errors in AI basis. As a result, the user-selectable accuracy for each of the coefficients in the FRS facilitates each of the 64 coefficients to have its precision set independently of others, avoiding the leakage of quantization noise between channels as is the case for published DCT designs. The proposed FRS uses two approaches based on (i) optimized Dempster-Macleod multipliers and (ii) expansion factor scaling. This architecture enables low-noise high-dynamic range applications in digital video processing that requires full control of the finite-precision computation of the 2-D DCT. The proposed architectures and FRS techniques are experimentally verified and validated using hardware implementations that are physically realized and verified on FPGA chip. Six designs, for 4-and 8-bit input word sizes, using the two proposed FRS schemes, have been designed, simulated, physically implemented and measured. The maximum clock rate and block-rate achieved among 8-bit input designs are 307.787 MHz and 38.47 MHz, respectively, implying a pixel rate of 8×307.787≈2.462 GHz if eventually embedded in a real-time video-processing system. The equivalent frame rate is about 1187.35 Hz for the image size of 1920×1080. All implementations are functional on a Xilinx Virtex-6 XC6VLX240T FPGA device.

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Section: -D Ai Dct Architecturementioning

confidence: 99%

Section: An 8-point Ai-encoded Arai Dct Corementioning

confidence: 99%

Section: An 8-point Ai-encoded Arai Dct Corementioning

confidence: 99%

mentioning

confidence: 99%

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A Row-Parallel 8$\,\times\,$8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

Madanayake

Cintra²,

Onen³

et al. 2012

IEEE Trans. Circuits Syst. Video Technol.

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“…In fact, the DCT is a robust approximation for the optimal Karhunen-Loève transform when first-order Markov signals, such as images, are considered [12,30,38].Indeed, the DCT has found application in several image and video coding schemes [5,12], such as JPEG [36], , , H.261 [23], H.263 [24], and H.264 [32, 46, 51].Through the decades signal processing literature has been populated with efficient methods for the DCT computation, collectively known as fast algorithms. This can be observed in several works with efficient hardware and software implementations, including [2,3,13,14,17,21,31,44]. Methods such as the Arai DCT algorithm [2] can greatly reduced the number of arithmetic operations required for the DCT evaluation.…”

mentioning

confidence: 99%

A digital hardware fast algorithm and FPGA-based prototype for a novel 16-point approximate DCT for image compression applications

Bayer

Cintra

Edirisuriya

et al. 2012

Meas. Sci. Technol.

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The discrete cosine transform (DCT) is the key step in many image and video coding standards. The 8-point DCT is an important special case, possessing several low-complexity approximations widely investigated. However, 16-point DCT transform has energy compaction advantages. In this sense, this paper presents a new 16-point DCT approximation with null multiplicative complexity. The proposed transform matrix is orthogonal and contains only zeros and ones. The proposed transform outperforms the well-know Walsh-Hadamard transform and the current state-of-the-art 16-point approximation. A fast algorithm for the proposed transform is also introduced. This fast algorithm is experimentally validated using hardware implementations that are physically realized and verified on a 40 nm CMOS Xilinx Virtex-6 XC6VLX240T FPGA chip for a maximum clock rate of 342 MHz. Rapid prototypes on FPGA for 8-bit input word size shows significant improvement in compressed image quality by up to 1-2 dB at the cost of only eight adders compared to the state-of-art 16-point DCT approximation algorithm in the literature [S. Bouguezel, M. O. Ahmad, and M. N. S. Swamy. A novel transform for image compression.

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New fast and area-efficient pipeline 3-D DCT architectures

Al-Azawi

Nibouche²,

Boussakta

et al. 2019

Digital Signal Processing

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The efficient implementation of 3-D transforms is a challenging task due to the computation complexity, memory and area requirements of such transforms. One important 3-D transform is the 3-D Discrete Cosine Transform (3-D DCT) used in many image and video processing systems. In this paper, two new pipeline architectures for the 3-D DCT computation using the 3-D DCT Vector-Radix algorithm (3-D DCT VR) are presented. These architectures are scalable and parameterisable with regards to different wordlengths and pipelining levels. Their arithmetic component requirements are reduced to the order of ( 2 ) in contrast with ( ) for 3-D DCT architectures in the literature, while at the same time they can keep similar or better area-time complexity.

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Algebraic integer based 8×8 2-D DCT architecture for digital video processing

Cited by 18 publications

References 5 publications

A Row-Parallel 8$\,\times\,$8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

A Row-Parallel 8$\,\times\,$8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

A digital hardware fast algorithm and FPGA-based prototype for a novel 16-point approximate DCT for image compression applications

New fast and area-efficient pipeline 3-D DCT architectures

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