A Row-Parallel 8$\,\times\,$8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

Abstract

An algebraic integer (AI) based time-multiplexed row-parallel architecture and two final-reconstruction step (FRS) algorithms are proposed for the implementation of bivariate AI-encoded 2-D discrete cosine transform (DCT). The architecture directly realizes an error-free 2-D DCT without using FRSs between row-column transforms, leading to an 8×8 2-D DCT which is entirely free of quantization errors in AI basis. As a result, the user-selectable accuracy for each of the coefficients in the FRS facilitates each of the 64 coefficients to have its precision set independently of others, avoiding the leakage of quantization noise between channels as is the case for published DCT designs. The proposed FRS uses two approaches based on (i) optimized Dempster-Macleod multipliers and (ii) expansion factor scaling. This architecture enables low-noise high-dynamic range applications in digital video processing that requires full control of the finite-precision computation of the 2-D DCT. The proposed architectures and FRS techniques are experimentally verified and validated using hardware implementations that are physically realized and verified on FPGA chip. Six designs, for 4-and 8-bit input word sizes, using the two proposed FRS schemes, have been designed, simulated, physically implemented and measured. The maximum clock rate and block-rate achieved among 8-bit input designs are 307.787 MHz and 38.47 MHz, respectively, implying a pixel rate of 8×307.787≈2.462 GHz if eventually embedded in a real-time video-processing system. The equivalent frame rate is about 1187.35 Hz for the image size of 1920×1080. All implementations are functional on a Xilinx Virtex-6 XC6VLX240T FPGA device.

A Single-Channel Architecture for Algebraic Integer-Based 8$\,\times\,$8 2-D DCT Computation

“…Additionally, we present a 2-D DCT architecture based on the improved 1-D transform. This 2-D constitutes of a single channel which provides improvements in terms of area and power consumption when compared with the four channel architecture described in [13]. We show that these improvements could be obtained without making any compromise in terms of accuracy.…”

“…1. This provides an improvement in terms of hardware resources when compared with the algorithm proposed in [13] and [9], which requires 21 additions and 2 shift operations. Although when only a single DCT is considered, the economy of one addition and two bit-shifting operations may seem modest, we note that in video processing systems, the 1-D DCT is performed many times (once per column, per row, per component, per 8×8 block, per frame).…”

“…In [13] an AI based architecture, where the reconstruction step occurs only at the end of the computation, was proposed. In other words, the reconstruction step was placed after both row-and column-wise transforms.…”

“…The decoding can be done in a tailored FRS where the AI basis is represented at the desired precision. Several FRS structures have been proposed, including schemes that employ Booth encoding [9] and the expansion factor method [13,15].…”

High throughput and energy efficient two‐dimensional inverse discrete cosine transform architecture

“…Regarding the power consumption, the comparison with previous FPGA implementations [24,39] shows that the proposed architecture has significantly lower normalised energy consumption and, therefore higher energy efficiency. In addition, with respect to the number of occupied slices, the proposed architecture has lower area demands.…”