With a combination of the static capacitance-voltage (C-V) and the capacitance transient (C-t) methods, the interface-state response in an Al 2 O 3 /n-GaN structure was investigated at temperatures ranging from 23 to 300 o C. We observed pronounced degradation of the static C-V curves measured at high temperatures, arising from the enhancement of charging/discharging rates of interface states at deeper energies within the bandgap of GaN. Faster responses with larger magnitudes also appeared in the time-dependent capacitance at high temperatures. From a simple analysis of the C-t results, we estimated the capture cross section of the states to be on the order of 10 -19 cm 2 .KEYWORDS: GaN, MIS, interface state, C-V, C-t, high temperature, capture cross section *E-mail address: hashi@rciqe.hokudai.ac.jpAn insulated-gate structure is very attractive for GaN-based high-efficiency power switching devices and high-power transistors operating at high frequency [1][2][3]. For realization of well-controlled and reliable insulated-gate structure, it is necessary to achieve an insulator-semiconductor (I-S) interface with a low density of electronic states [1,4,5]. To characterize the properties of interface states, a static capacitance-voltage (C-V) method is generally used.In the case of GaN I-S structures, however, it is difficult, from the room-temperature (RT) C-V method, to gain information on the interface states located near midgap or deeper, because the wide-gap nature of GaN makes the time constant for carrier emission from deeper states extremely large at RT. In this case, as schematically shown in Fig. 1, the charging state remains almost unchanged while the gate bias is swept in the C-V measurements even if the interface states have high densities. Thus, it should be pointed out that the RT C-V method only provides the response of the states with a limited energy range near the conduction band minimum or the valence band maximum. At higher temperatures, on the other hand, the deeper interface states can produce larger amounts of charges, particularly under bias conditions for depletion. Since high-power operation significantly increases the channel temperature in the GaN-based transistors [6][7][8], such interface charges may impede