ALD Options for Si-integrated Ultrahigh-density Decoupling Capacitors in Pore and Trench Designs

Abstract

Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publicationCitation for published version (APA): Roozeboom, F., Klootwijk, J. H., Verhoeven, J. F. C., Heuvel, van den, F. C., Dekkers, W., Heil, S. B. S., ... Blin, D. (2007). ALD options for Si-integrated ultrahigh-density decoupling capacitors in pore and trench designs. ECS Transactions, 3(15), 173-181. DOI: 10.1149/1.2721486 General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. This paper reviews the options of using Atomic Layer Deposition (ALD) in passive and heterogeneous integration. The miniaturization intended by both integration schemes aim at Si-based integration for the former and at die stacking in a compact System-in-Package for the latter.In future Si-based integrated passives a next miniaturization step in trench capacitors requires the use of multiple 'classical' MOS layer stacks and the use of so-called high-k dielectrics (based on HfO 2 , etc.) and novel conductive layers like TiN, etc. to compose MIS and MIM stacks in 'trench' and 'pore' capacitors with capacitance densities exceeding 200 nF/mm 2 . One of the major challenges in realizing ultrahigh-density trench capacitors is to find an attractive pore lining and filling fabrication technology at reasonable cost and reaction rate as well as low temperature (for back-end processing freedom). As the deposition for the dielectric and conductive layers should be highly uniform, step-conformal and lowtemperature (≤ 400 °C), ALD is an enabling technology here, by virtue of the self-limiting mechanism of this layer-by-layer deposition technique.This article discusses first a f...

Silicon Capacitors with extremely high stability and reliability ideal for high temperature applications

“…Capacitors with Oxide/Nitride /Oxide dielectric stacks and polysilicon top electrodes yield a capacitance density of 250nF/mm² ,an electrical breakdown voltage of 11V and very low leakage current (<1nA at the working voltage).These capacitors also show low loss factors (equivalent series resistance ESR < 150mohms and equivalent series inductance ESL < 250pH). Last year , IPDiA released this process for mass production , launched derivative options with higher breakdown voltage ( figure1) and demonstrated the feasibility to reach 550nF/mm² at 11 volts breakdown .Obviously this huge capacitance density increase is achievable thanks to higher k-dielectric layers and to the ALD (atomic layer deposition ) enabling excellent step coverage of the deposited layer [2]. These capacitors in ultra deep trenches have been developed and implemented in a process called PICS (Passive Integration Connective Substrate ) in order to integrate passive components such as high-Q inductors , resistors , accurate planar MIM capacitors and trench MOS capacitors for many applications like for example switched capacitor voltage multiplier or buck converter , decoupling and filtering .This process is providing a fully CMOS compatible solution for the integration on chip or multiple chip module .Its potential for miniaturization means smaller component size , reduced manufacturing costs per product ,low power consumption and integration of more basic functions into one product.…”

Towards tilt-free in plasma etching

“…Plasma etching is a process that matters for microstructures manufacturing in both scientific and industrial communities [1,2], which can be widely applied in various devices (such as microelectromechanical systems (MEMS) [3,4], capacitors [5,6], metal-oxide-semiconductor field effect transistors (MOSFETs) [7,8], and memory devices [9,10]) and device related processes (such as advanced packaging [11,12] and device isolation [13,14]). In detail, MEMS gyroscope based on the Coriolis force principle contains parallel plate capacitor accelerators in two independent directions, and the higher depth/verticality of the silicon microstructure can increase the 4 Contributed equally to this work.…”

“…accuracy of the sensor [3]. Similarly, the higher depth/verticality of the silicon microstructure in silicon capacitors can also increase the capacitance and the use efficient of device space [5,6], and plasma etching is considered to be the mainstream method for obtaining high aspect ratio microstructures [15,16]. When the gate structure in MOSFET is developed from planar architecture to trench gate (fabricated by plasma etching), the channel electron scattering can be inhibited to increase the carrier mobility, and the short channel effect can be improved [7,8].…”

The application of the scallop nanostructure in deep silicon etching

“…Micro/nanostructures with high aspect ratios in silicon wafers [1][2][3][4][5] are of great significance in microelectronic device fabrication, such as micro-electro-mechanical systems (MEMS) [6,7], power chips [8,9], silicon capacitors [10,11] and advanced packaging [12,13]. To obtain such deep and vertical silicon microstructures, plasma etching with a time division multiplex process developed by Robert Bosch GmbH [14] is primarily employed.…”